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(R)
STLC5465B
MULTI-HDLC WITH n x 64 SWITCHING MATRIX ASSOCIATED
. . . . . . . . . . . . . . .
32 TxHDLCs WITH BROADCASTING CAPABILITY AND/OR CSMA/CR FUNCTION WITH AUTOMATIC RESTART IN CASE OF TX FRAME ABORT 32 RxHDLCs INCLUDING ADDRESS RECOGNITION 16 COMMAND/INDICATE CHANNELS (4 OR 6-BIT PRIMITIVE) 16 MONITOR CHANNELS PROCESSED IN ACCORDANCE WITH GCI OR V* 256 x 256 SWITCHING MATRIX WITHOUT BLOCKING AND WITH TIME SLOT SEQUENCE INTEGRITY AND LOOPBACK PER BIDIRECTIONAL CONNECTION DMA CONTROLLER FOR 32 Tx CHANNELS AND 32 Rx CHANNELS HDLCs AND DMA CONTROLLER ARE CAPABLE OF HANDLING A MIX OF LAPD, LAPB, SS7,CAS AND PROPRIETARY SIGNALLINGS EXTERNAL SHARED MEMORY ACCESS BETWEEN DMA CONTROLLER AND MICROPROCESSOR SINGLE MEMORY SHARED BETWEEN n x MULTI-HDLCs AND SINGLE MICROPROCESSOR ALLOWS TO HANDLE n x 32 CHANNELS BUS ARBITRATION INTERFACE FOR VARIOUS 8,16 OR 32 BIT MICROPROCESSORS RAM CONTROLLER ALLOWS TO INTERFACE UP TO : -16 MEGABYTES OF DYNAMIC RAM OR -1 MEGABYTE OF STATIC RAM INTERRUPT CONTROLLER TO STORE AUTOMATICALLY EVENTS IN SHARED MEMORY PQFP160 PACKAGE BOUNDARY SCAN FOR TEST FACILITY
DESCRIPTION The STLC5465B is a Subscriber line interface card controller for Central Office, Central Exchange, NT2 and PBX capable of handling : - 16 U Interfaces or - 2 Megabits line interface cards or - 16 SLICs (Plain Old Telephone Service) or - Mixed analogue and digital Interfaces (SLICs or U Interfaces) or - 16 S Interfaces - Switching Network with centralized processing
PQFP160 (Plastic Quad Flat Pack) ORDERING NUMBER : STLC5465B
June 1999
1/101
STLC5465B
TABLE OF CONTENTS I - PIN INFORMATION . . . . . . . . . . . . . . . . . . . I.1 - Pin Connections . . . . . . . . . . . . . . . . . . I.2 - Pin Description . . . . . . . . . . . . . . . . . . . I.3 - Pin Definition . . . . . . . . . . . . . . . . . . . . I.3.1 - Input Pin Definition . . . . . . . . . . . . . . . . I.3.2 - Output Pin Definition . . . . . . . . . . . . . . . I.3.3 - Input/Output Pin Definition . . . . . . . . . . . . II - BLOCK DIAGRAM . . . . . . . . . . . . . . . . . . . III - FUNCTIONAL DESCRIPTION . . . . . . . . . . . . . III.1 - The Switching Matrix N x 64 KBits/S . . . . . . . III.1.1 - Function Description . . . . . . . . . . . . . . III.1.2 - Architecture of the Matrix . . . . . . . . . . . . III.1.3 - Connection Function . . . . . . . . . . . . . . III.1.4 - Loop Back Function . . . . . . . . . . . . . . . III.1.5 - Delay through the Matrix . . . . . . . . . . . . III.1.5.1 - Variable Delay Mode . . . . . . . . . . . . . III.1.5.2 - Sequence Integrity Mode . . . . . . . . . . . III.1.6 - Connection Memory . . . . . . . . . . . . . . . III.1.6.1 - Description . . . . . . . . . . . . . . . . . . III.1.6.2 - Access to Connection Memory . . . . . . . . III.1.6.3 - Access to Data Memory . . . . . . . . . . . . III.1.6.4 - Switching at 32 Kbit/s . . . . . . . . . . . . . III.1.6.5 - Switching at 16 kbit/s . . . . . . . . . . . . . III.2 - HDLC Controller . . . . . . . . . . . . . . . . . . III.2.1 - Function Description . . . . . . . . . . . . . . III.2.1.1 - Format of the HDLC Frame . . . . . . . . . . III.2.1.2 - Composition of an HDLC Frame . . . . . . . III.2.1.3 - Description and Functions of the HDLC Bytes III.2.2 - CSMA/CR Capability . . . . . . . . . . . . . . III.2.3 - Time Slot Assigner Memory . . . . . . . . . . . III.2.4 - Data Storage Structure . . . . . . . . . . . . . III.2.4.1 - Reception . . . . . . . . . . . . . . . . . . . III.2.4.2 - Transmission . . . . . . . . . . . . . . . . . III.2.4.3 - Frame Relay . . . . . . . . . . . . . . . . . III.2.5 - Transparent Modes . . . . . . . . . . . . . . . III.2.6 - Command of the HDLC Channels . . . . . . . III.2.6.1 - Reception Control . . . . . . . . . . . . . . . III.2.6.2 - Transmission Control . . . . . . . . . . . . . III.3 - C/I and Monitor . . . . . . . . . . . . . . . . . . III.3.1 - Function Description . . . . . . . . . . . . . . III.3.2 - GCI and V* Protocol . . . . . . . . . . . . . . . III.3.3 - Structure of the Treatment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Page ..8 .. 8 ..9 . . 13 . . 13 . . 13 . . 13 . . 14 . . 15 . . 15 . . 15 . . 15 . . 15 . . 15 . . 17 . . 17 . . 17 . . 21 . . 21 . . 21 . . 21 . . 21 . . 21 . . 25 . . 25 . . 25 . . 25 . . 26 . . 26 . . 27 . . 27 . . 27 . . 27 . . 27 . . 29 . . 29 . . 29 . . 29 . . 29 . . 29 . . 30 . . 30
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TABLE OF CONTENTS (continued) III - FUNCTIONAL DESCRIPTION (continued) III.3.4 - CI and Monitor Channel Configuration . . . . . . . . . . . . . . III.3.5 - CI and Monitor Transmission/Reception Command . . . . . . . III.4 - Microprocessor Interface . . . . . . . . . . . . . . . . . . . . . . III.4.1 - Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . III.4.2 - Exchange with the shared memory . . . . . . . . . . . . . . . . III.4.2.1 - Write FIFO . . . . . . . . . . . . . . . . . . . . . . . . . . . III.4.2.2 - Read Fetch Memory . . . . . . . . . . . . . . . . . . . . . . III.4.3 - Definition of the Interface for the different microprocessors . . . . III.5 - Memory Interface . . . . . . . . . . . . . . . . . . . . . . . . . . III.5.1 - Function Description . . . . . . . . . . . . . . . . . . . . . . . III.5.2 - Choice of memory versus microprocessor and capacity required III.5.3 - Memory Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . III.5.4 - SRAM interface . . . . . . . . . . . . . . . . . . . . . . . . . . III.5.5 - DRAM Interface . . . . . . . . . . . . . . . . . . . . . . . . . . III.5.4.2 - 512K x n SRAM . . . . . . . . . . . . . . . . . . . . . . . . . III.5.5.2 - 1M x n DRAM Signals . . . . . . . . . . . . . . . . . . . . . . III.5.5.3 - 4M x n DRAM Signals . . . . . . . . . . . . . . . . . . . . . . III.6 - Bus Arbitration . . . . . . . . . . . . . . . . . . . . . . . . . . . III.7 - Clock Selection and Time Synchronization . . . . . . . . . . . . . III.7.1 - Clock Distribution Selection and Supervision . . . . . . . . . . . III.7.2 - VCXO Frequency Synchronization . . . . . . . . . . . . . . . . III.8 - Interrupt Controller . . . . . . . . . . . . . . . . . . . . . . . . . III.8.1 - Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . III.8.2 - Operating Interrupts (INT0 Pin) . . . . . . . . . . . . . . . . . . III.8.3 - Time Base Interrupts (INT1 Pin) . . . . . . . . . . . . . . . . . III.8.4 - Emergency Interrupts (WDO Pin) . . . . . . . . . . . . . . . . . III.8.5 - Interrupt Queues . . . . . . . . . . . . . . . . . . . . . . . . . III.9 - Watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . III.10 - Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . III.11 - Boundary Scan . . . . . . . . . . . . . . . . . . . . . . . . . . IV - DC SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . IV.1 - Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . IV.2 - Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . IV.3 - Recommended DC Operating Conditions . . . . . . . . . . . . . IV.4 - TTL Input DC Electrical Characteristics . . . . . . . . . . . . . . . IV.5 - CMOS Output DC Electrical Characteristics . . . . . . . . . . . . IV.6 - Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V - CLOCK TIMING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V.1 - Synchronization Signals delivered by the system . . . . . . . . . . V.2 - TDM Synchronization . . . . . . . . . . . . . . . . . . . . . . . . V.3 - GCI Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . V.4 - V* Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..... ..... ..... ..... ..... ..... ..... ..... ..... ..... ..... ..... ..... ..... ..... ..... ..... ..... ..... ..... ..... ..... ..... ..... ..... ..... ..... ..... ..... ..... ..... ..... ..... ..... ..... ..... ..... ..... ..... ..... ..... ..... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ...
Page . . . . . 30 . . . . . 30 . . . . . 34 . . . . . 34 . . . . . 35 . . . . . 35 . . . . . 35 . . . . . 35 . . . . . 38 . . . . . 38 . . . . . 38 . . . . . 38 . . . . . 39 . . . . . 39 . . . . . 39 . . . . . 40 . . . . . 40 . . . . . 40 . . . . . 41 . . . . . 41 . . . . . 41 . . . . . 42 . . . . . 42 . . . . . 42 . . . . . 42 . . . . . 42 . . . . . 42 . . . . . 43 . . . . . 43 . . . . . 43 . . . . . 44 . . . . . 44 . . . . . 44 . . . . . 44 . . . . . 44 . . . . . 44 . . . . . 44 . . . . . 45 . . . . . 45 . . . . . 46 . . . . . 47 . . . . . 48
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TABLE OF CONTENTS (continued) V1 - MEMORY TIMING . . . . . . . . . . . . . . . . . . . . . . . . . . . VI.1 - Dynamic Memories . . . . . . . . . . . . . . . . . . . . . . . . VI.2 - Static Memories . . . . . . . . . . . . . . . . . . . . . . . . . . VII - MICROPROCESSOR TIMING . . . . . . . . . . . . . . . . . . . . . VII.1 - ST9 Family MOD0=1, MOD1=0, MOD2=0 . . . . . . . . . . . . VII.2 - ST10/C16x mult. A/D, MOD0 = 1, MOD1 = 0, MOD2 = 1 . . . . VII.3 - ST10/C16x demult. A/D, MOD0 = 1, MOD1 = 0, MOD2 = 1 . . . VII.4 - 80C188 MOD0=1, MOD1=1, MOD2=0 . . . . . . . . . . . . . . VII.5 - 80C186 MOD0=1, MOD1=1, MOD2=1 . . . . . . . . . . . . . . VII.6 - 68000 MOD0=0, MOD1=0, MOD2=1 . . . . . . . . . . . . . . VII.7 - 68020 MOD0=0, MOD1=0, MOD2=0 . . . . . . . . . . . . . . . VII.8 - Token Ring Timing . . . . . . . . . . . . . . . . . . . . . . . . VII.9 - Master Clock Timing . . . . . . . . . . . . . . . . . . . . . . . VIII - INTERNAL REGISTERS . . . . . . . . . . . . . . . . . . . . . . . VIII.1 - Identification and Dynamic Command Register - IDCR (00)H . . VIII.2 - General Configuration - GCR (02)H . . . . . . . . . . . . . . . VIII.3 - Input Multiplex Configuration Register 0 - IMCR0 (04)H . . . . VIII.4 - Input Multiplex Configuration Register 1 - IMCR1 (06)H . . . . VIII.5 - Output Multiplex Configuration Register 0 - OMCR0 (08)H . . . VIII.6 - Output Multiplex Configuration Register 1 - OMCR1 (0A)H . . . VIII.7 - Switching Matrix Configuration Register - SMCR (0C)H . . . . VIII.8 - Connection Memory Data Register - CMDR (0E)H . . . . . . . VIII.9 - Connection Memory Address Register - CMAR (10)H . . . . . VIII.10 - Sequence Fault Counter Register - SFCR (12)H . . . . . . . VIII.11 - Time Slot Assigner Address Register - TAAR (14)H . . . . . . VIII.12 - Time Slot Assigner Data Register - TADR (16)H . . . . . . . VIII.13 - HDLC Transmit Command Register - HTCR (18)H . . . . . . VIII.14 - HDLC Receive Command Register - HRCR (1A)H . . . . . . VIII.15 - Address Field Recognition Address Register - AFRAR (1C)H . VIII.16 - Address Field Recognition Data Register - AFRDR (1E)H . . . VIII.17 - Fill Character Register - FCR (20)H . . . . . . . . . . . . . . VIII.18 - GCI Channels Definition Register 0 - GCIR0 (22)H . . . . . . VIII.19 - GCI Channels Definition Register 1 - GCIR1 (24)H . . . . . . VIII.20 - GCI Channels Definition Register 2 - GCIR2 (26)H . . . . . . VIII.21 - GCI Channels Definition Register 3 - GCIR3 (28)H . . . . . . VIII.22 - Transmit Command / Indicate Register - TCIR (2A)H . . . . . Transmit Command/Indicate Register (after reading) . . . . . VIII.23 - Transmit Monitor Address Register - TMAR (2C)H . . . . . . Transmit Monitor Address Register (after reading) . . . . . . . VIII.24 - Transmit Monitor Data Register - TMDR (2E)H . . . . . . . . VIII.25 - Transmit Monitor Interrupt Register - TMIR (30)H . . . . . . . VIII.26 - Memory Interface Configuration Register - MICR (32)H . . . . Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Page . . . 49 . . . 49 . . . 51 . . . 53 . . . 53 . . . 55 . . . 57 . . . 59 . . . 61 . . . 63 . . . 65 . . . 67 . . . 67 . . . 68 . . . 68 . . . 68 . . . 70 . . . 70 . . . 71 . . . 71 . . . 71 . . . 74 . . . 77 . . . 79 . . . 79 . . . 80 . . . 81 . . . 82 . . . 84 . . . 84 . . . 84 . . . 84 . . . 85 . . . 85 . . . 85 . . . 86 . . . 86 . . . 87 . . . 87 . . . 88 . . . 88 . . . 88 . . . 89
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TABLE OF CONTENTS (continued) VIII - INTERNAL REGISTERS (continued) VIII.27 - Initiate Block Address Register - IBAR (34)H . . . . VIII.28 - Interrupt Queue Size Register - IQSR (36)H . . . . . VIII.29 - Interrupt Register - IR (38)H . . . . . . . . . . . . . VIII.30 - Interrupt Mask Register - IMR (3A)H . . . . . . . . . VIII.31 - Timer Register - TIMR (3C)H . . . . . . . . . . . . VIII.32 - Test Register - TR (3E)H . . . . . . . . . . . . . . . IX - EXTERNAL REGISTERS . . . . . . . . . . . . . . . . . . . IX.1 - Initialization Block in External Memory . . . . . . . . . IX.2 - Receive Descriptor . . . . . . . . . . . . . . . . . . . IX.2.1 - Bits written by the Microprocessor only . . . . . . . . IX.2.2 - Bits written by the Rx DMAC only . . . . . . . . . . . IX.2.3 - Receive Buffer . . . . . . . . . . . . . . . . . . . . IX.3 - Transmit Descriptor . . . . . . . . . . . . . . . . . . . IX.3.1 - Bits written by the Microprocessor only . . . . . . . . IX.3.2 - Bits written by the DMAC only . . . . . . . . . . . . IX.3.3 - Transmit Buffer . . . . . . . . . . . . . . . . . . . . IX.4 - Receive & Transmit HDLC Frame Interrupt . . . . . . . IX.5 - Receive Command / Indicate Interrupt . . . . . . . . . IX.5.1 - Receive Command / Indicate Interrupt when TSV = 0 IX.5.2 - Receive Command / Indicate Interrupt when TSV = 1 IX.6 - Receive Monitor Interrupt . . . . . . . . . . . . . . . . IX.6.1 - Receive Monitor Interrupt when TSV = 0 . . . . . . . IX.6.2 - Receive Monitor Interrupt when TSV = 1 . . . . . . . X - PQFP160 PACKAGE MECHANICAL DATA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Page . . . . . . . . . . . . . . . . . . . . . . . . . 90 . 90 . 91 . 92 . 92 . 92 . 93 . 93 . 94 . 94 . 94 . 94 . 95 . 95 . 96 . 96 . 96 . 97 . 97 . 98 . 98 . 98 . 99 100
5/101
STLC5465B
LIST OF FIGURES I - PIN INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . II - BLOCK DIAGRAM . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 1 : General Block Diagram . . . . . . . . . . . . . . . . . . III - FUNCTIONAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . Figure 2 : Switching Matrix Data Path . . . . . . . . . . . . . . . . Figure 3 : Unidirectional and Bidirectional Connections . . . . . . . Figure 4 : Loop Back . . . . . . . . . . . . . . . . . . . . . . . . . Figure 5 : Variable Delay through the matrix with ITDM = 1 . . . . . Figure 6 : Variable Delay through the matrix with ITDM = 0 . . . . . Figure 7 : Constant Delay through the matrix with SI = 1 . . . . . . . Figure 8: Downstream Switching at 32kb/s . . . . . . . . . . . . . . Figure 9: Upstream Switching at 32kb/s . . . . . . . . . . . . . . . Figure 10: Upstream and Downstream Switching at 16kb/s . . . . . Figure 11 : HDLC and DMA Controller Block Diagram . . . . . . . . Figure 12 : Structure of the Receive Circular Queue . . . . . . . . . Figure 13 : Structure of the Transmit Circular Queue . . . . . . . . Figure 14 : D, C/I and Monitor Channel Path . . . . . . . . . . . . . Figure 15: GCI channel to/from ISDN Channel . . . . . . . . . . . . Figure 16: From GCI Channels to ISDN Channels . . . . . . . . . . Figure 17: From ISDN channels to GCI Channels . . . . . . . . . . Figure 17.1: Write FIFO and Fetch Memories . . . . . . . . . . . . Figure 18 : Multi-HDLC connected to P with multiplexed buses . . Figure 19 : Multi-HDLC connected to P with non-multiplexed buses Figure 20 : Microprocessor Interface for INTEL 80C188 . . . . . . . Figure 21 : Microprocessor Interface for INTEL 80C186 . . . . . . . Figure 22 : Microprocessor Interface for MOTOROLA 68000 . . . . Figure 23 : Microprocessor Interface for MOTOROLA 68020 . . . . Figure 24 : Microprocessor Interface for ST9 . . . . . . . . . . . . . Figure 25 : n x 128K x 16 SRAM Memory Organization . . . . . . . Figure 26 : 512K x 8 SRAM Circuit Memory Organization . . . . . . Figure 27 : 256K x 16 DRAM Circuit Organization . . . . . . . . . . Figure 28 : 1M x 16 DRAM Circuit Organization . . . . . . . . . . . Figure 29 : 4M x 16 DRAM Circuit Organization . . . . . . . . . . . Figure 30 : Chain of n Multi-HDLC Components . . . . . . . . . . . Figure 31 : MHDLC Clock Generation . . . . . . . . . . . . . . . . Figure 32 : VCXO Frequency Synchronization . . . . . . . . . . . . Figure 33 : The Three Circular Interrupt Memories . . . . . . . . . . IV - DC SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . V - CLOCK TIMING . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 34 : Clocks received and delivered by the Multi-HDLC . . . . Figure 35 : Synchronization Signals received by the Multi-HDLC . . Figure 36 : GCI Synchro Signal delivered by the Multi-HDLC . . . . Figure 37 : V* Synchronization Signal delivered by the Multi-HDLC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Page .. . 8 . . . 14 . . . 14 . . . 15 . . . 16 . . . 17 . . . 17 . . . 18 . . . 19 . . . 20 . . . 22 . . . 23 . . . 24 . . . 25 . . . 28 . . . 28 . . . 31 . . . 32 . . . 33 . . . 34 . . . 35 . . . 36 . . . 36 . . . 36 . . . 36 . . . 37 . . . 37 . . . 37 . . . 39 . . . 39 . . . 39 . . . 40 . . . 40 . . . 40 . . . 41 . . . 42 . . . 43 . . . 44 . . . 45 . . . 45 . . . 46 . . . 47 . . . 48
6/101
STLC5465B
LIST OF FIGURES (continued) VI - MEMORY TIMING . . . . . . . . . . . . . . . . . . . . . . . . Figure 38 : Dynamic Memory Read Signals from the Multi-HDLC Figure 39 : Dynamic Memory Write Signals from the Multi-HDLC Figure 40 : Static Memory Read Signals from the Multi-HDLC . . Figure 41 : Static Memory Write Signals from the Multi-HDLC . . Figure 42 : ST9 Read Cycle . . . . . . . . . . . . . . . . . . . VII - MICROPROCESSOR TIMING . . . . . . . . . . . . . . . . . . Figure 43 : ST9 Write Cycle . . . . . . . . . . . . . . . . . . . Figure 44 : ST10 (C16x) Read Cycle; Multiplexed A/D . . . . . . Figure 45 : ST10 (C16x) Write Cycle; Multiplexed A/D . . . . . . Figure 46 : ST10 (C16x) Read Cycle; Demultiplexed A/D . . . . Figure 47 : ST10 (C16x) Write Cycle; Demultiplexed A/D . . . . Figure 48 : 80C188 Read Cycle . . . . . . . . . . . . . . . . . Figure 49 : 80C188 Write Cycle . . . . . . . . . . . . . . . . . Figure 50 : 80C186 Read Cycle . . . . . . . . . . . . . . . . . Figure 51 : 80C186 Write Cycle . . . . . . . . . . . . . . . . . Figure 52 : 68000 Read Cycle . . . . . . . . . . . . . . . . . . Figure 53 : 68000 Write Cycle . . . . . . . . . . . . . . . . . . Figure 54 : 68020 Read Cycle . . . . . . . . . . . . . . . . . . Figure 55 : 68020 Write Cycle . . . . . . . . . . . . . . . . . . Figure 56 : Token Ring . . . . . . . . . . . . . . . . . . . . . . Figure 57 : Master Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Page . . . . . . . . . . . . . . . . . . . . . . . 49 . 49 . 50 . 51 . 52 . 53 . 53 . 54 . 55 . 56 . 57 . 58 . 59 . 60 . 61 . 62 . 63 . 64 . 65 . 66 . 67 . 67
7/101
STLC5465B
I - PIN INFORMATION I.1 - Pin Connections
ADM14 ADM13 ADM12 ADM11 ADM10 NTEST ADM9 ADM8 ADM7 ADM6 ADM5 ADM4 ADM3 ADM2 ADM1 ADM0 DM15 DM14 DM13 DM12 DM11 DM10 DM9 DM8 DM7 DM6 DM5 DM4 DM3 DM2 DM1 DM0 VDD VDD VDD VDD 121 VSS VSS VSS VSS 122
160
159
158
157
156
155
154
153
152
151
150
149
148
147
146
145
144
143
142
141
140
139
138
137
136
135
134
133
132
131
130
129
128
127
126
125
124
123
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
NRESET XTAL1 XTAL2 WDO CB EC VCXO IN VCXO OUT DCLK CLOCKA CLOCKB FRAMEA FRAMEB VDD VSS FS FSCG FSCV PSS DIN0 DIN1 DIN2 DIN3 DIN4 DIN5 DIN6 DIN7 DIN8 VDD VSS DOUT0 DOUT1 DOUT2 DOUT3 DOUT4 DOUT5 DOUT6 DOUT7 NDIS NTRST 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79
NCE7 NRAS3/NCE6 NCE5 NRAS2/NCE4 NCAS1/NCE3 NRAS1/NCE2 NCAS0/NCE1 NRAS0/NCE0 NOE NWE TRO TRI VSS VDD D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 VSS VDD A23/ADM18 A22/ADM17 A21/ADM16 A20/ADM15 A19 A18 A17 A16 80
120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
A0/AD0
A1/AD1
A2/AD2
A3/AD3
A4/AD4
A5/AD5
A6/AD6
A7/AD7
A8/AD8
NDTACK
A9/AD9
READY
A10/AD10
A11/AD11
A12/AD12
A13/AD13
A14/AD14
NBHE/NUDS
R/W / NWR
A15/AD15
NAS/ALE
NDS/NRD
MOD0
MOD1
MOD2
TDI
NLDS
NCS0
NCS1
TMS
TDO
TCK
INT0
INT1
VSS
VSS
VDD
VDD
VDD
VSS
8/101
5464-01.EPS
STLC5465B
I - PIN INFORMATION (continued) I.2 - Pin Description
Pin N 14 15 29 30 45 46 61 62 73 74 89 90 107 108 121 122 133 134 145 146 158 159 CLOCKS 2 3 7 8 10 11 12 13 9 XTAL1 XTAL2 VCXO IN VCXO OUT CLOCKA CLOCKB FRAMEA FRAMEB DCLK I O I3 O4 I3 I3 I3 I3 O8 Crystal 1. A clock pulse at fMin. = 32000kHz can be applied to this input (or one pin of two crystal pins) with : -50.10-6 < f < +50.10-6. Crystal 2. If the internal crystal oscillator is used, the second crystal pin is applied to this output. VCXO input signal. This signal is compared to clock A(or B) selected inside the Multi-HDLC. VCXO error signal. This pin delivers the result of the comparison. Input Clock A (4096kHz or 8192kHz) Input Clock B (4096kHz or 8192kHz) Clock A at 8kHz Clock B at 8kHz Data Clock issued from Input Clock A (or B). This clock is delivered by the circuit at 4096kHz (or 2048kHz). DOUT0/7 are transmitted on the rising edge of this signal. DIN0/7 are sampled on the falling edge of this signal. Frame synchronization for GCI at 8kHz. This clock is issued from FRAME A (or B). Frame synchronization for V Star at 8kHz Frame synchronization.This signal synchronizes DIN0/7 and DOUT0/7. Programmable synchronization Signal. The PS bit of connection memory is read in real time.
I3 = I1 + Hysteresis ; I4 = I3 + Pull-up ; O8 = Output CMOS 8mA, "1" and "0" at Low Impedance ; O8DT = Output CMOS 8mA, Open Drain or Tristate ;
Symbol VDD1 VSS1 VDD2 VSS2 VDD3 VSS3 VDD4 VSS4 VDD5 VSS5 VDD6 VSS6 VDD7 VSS7 VDD8 VSS8 VDD9 VSS9 VDD10 VSS10 VDD11 VSS11
Type Power Ground Power Ground Power Ground Power Ground Power Ground Power Ground Power Ground Power Ground Power Ground Power Ground Power Ground DC supply DC ground DC supply DC ground DC supply DC ground DC supply DC ground DC supply DC ground DC supply DC ground DC supply DC ground DC supply DC ground DC supply DC ground DC supply DC ground DC supply DC ground (Total 22)
Function
POWER PINS (all the power and ground pins must be connected)
17 18 16 19
FSCG FSCV* FS PSS
O8 O8 I3 O8
Type : I1 = Input TTL ; I2 = I1 + Pull-up ; O4 = Output CMOS 4mA ; O4T = O4 + Tristate ; O8D = Output CMOS 8mA, Open Drain ; O8T = Output CMOS 8mA, Tristate I1 and I3 must be connected to VDD and VSS if not used
9/101
STLC5465B
I - PIN INFORMATION (continued) I.2 - Pin Description (continued)
Pin N Symbol Type Function TIME DIVISION MULTIPLEXES (TDM) 20 21 22 23 24 25 26 27 28 31 32 33 34 35 36 37 38 39 5 6 DIN0 DIN1 DIN2 DIN3 DIN4 DIN5 DIN6 DIN7 DIN8 DOUT0 DOUT1 DOUT2 DOUT3 DOUT4 DOUT5 DOUT6 DOUT7 NDIS CB EC I1 I1 I1 I1 I1 I1 I1 I1 I1 O8DT O8DT O8DT O8DT O8DT O8DT O8DT O8DT I1 O8D I1 TDM0 Data Input 0 TDM1 Data Input 1 TDM2 Data Input 2 TDM3 Data Input 3 TDM4 Data Input 4 TDM5 Data Input 5 TDM6 Data Input 6 TDM7 Data Input 7 TDM8 Data Input 8 TDM0 Data Output 0 TDM1 Data Output 1 TDM2 Data Output 2 TDM3 Data Output 3 TDM4 Data Output 4 TDM5 Data Output 5 TDM6 Data Output 6 TDM7 Data Output 7 DOUT 0/7 Not Disable. When this pin is at 0V, the Data Output 0/7 are at high impedance. Wired at VDD if not used. Contention Bus for CSMA/CR Echo
BOUDARY SCAN 40 41 42 43 44 NTRST TMS TDI TDO TCK I4 I2 I2 O4 I2 Reset for boundary scan Mode Selection for boundary scan Input Data for boundary scan Output Data for boundary scan Clock for boundary scan
MICROPROCESSOR INTERFACE 58 59 60 1 47 48 49 50 4 MOD0 MOD1 MOD2 NRESET NCS0 NCS1 INT0 INT1 WDO I1 I1 I1 I3 I3 I3 O4 O4 O4 1 1 0 1 1 1 0 0 1 0 0 0 1 0 0 1 0 1 0 1 1
80C188 80C186 68000 68020 ST9 Circuit Reset
ST10m ST10Nm
Chip Select 0 : internal registers are selected Chip Select 1 : external memory is selected Interrupt generated by HDLC, RxC/I or RxMON. Active high. Interrupt1.This pin goes to 5V when the selected clock A (or B) has disappeared ; 250s after reset this pin goes to 5V also if clock A is not present. Watch Dog Output.This pin goes to 5V during 1ms when the microprocessor has not reset the Watch Dog during the programmable time.
I3 = I1 + Hysteresis ; I4 = I3 + Pull-up ; O8 = Output CMOS 8mA, "1" and "0" at Low Impedance ; O8DT = Output CMOS 8mA, Open Drain or Tristate ;
Type : I1 = Input TTL ; I2 = I1 + Pull-up ; O4 = Output CMOS 4mA ; O4T = O4 + Tristate ; O8D = Output CMOS 8mA, Open Drain ; O8T = Output CMOS 8mA, Tristate
10/101
STLC5465B
I - PIN INFORMATION (continued) I.2 - Pin Description (continued)
Pin N 51 52 53 54 55 56 57 63 64 65 66 67 68 69 70 71 72 75 76 77 78 79 80 81 82 83 84 85 86 87 88 91 92 93 94 95 96 97 98 99 Symbol SIZE0/NLDS SIZE1/NBHE/NUDS NDSACK0/NDTACK NDSACK1/READY NAS/ALE R/W / NWR NDS/NRD A0/AD0 A1/AD1 A2/AD2 A3/AD3 A4/AD4 A5/AD5 A6/AD6 A7/AD7 A8/AD8 A9/AD9 A10/AD10 A11/AD11 A12/AD12 A13/AD13 A14/AD14 A15/AD15 A16 A17 A18 A19 A20/ADM15 A21/ADM16 A22/ADM17 A23/ADM18 DO D1 D2 D3 D4 D5 D6 D7 D8 Type I3 I3 O8T O8T I3 I3 I3 I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I1 I1 I1 I1 I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O Function Transfer Size0 (68020)/Lower Data Strobe (68000) Transfer Size1 (68020)/Bus High Enable (Intel) / Upper Data Strobe (68000) Data Strobe, Acknowledge and Size0 (68020)/Data Transfer Acknowledge (68000) Data Strobe, Acknowledge and Size0 (68020)/Data Transfer Acknowledge (Intel) Address Strobe(Motorola) / Addresss Latch Enable(Intel) Read/Write (Motorola / Write(Intel) Data Strobe (Motorola 68020); at Vdd for 68000/Read Data (Intel) Address bit 0 (Motorola 68020); at Vdd for 68000 / Address/Data bit 0 (Intel) Address bit 1 (Motorola) / Address/Data bit 1 (Intel) Address bit 2 (Motorola) / Address/Data bit 2 (Intel) Address bit 3 (Motorola) / Address/Data bit 3 (Intel) Address bit 4 (Motorola) / Address/Data bit 4 (Intel) Address bit 5 (Motorola) / Address/Data bit 5 (Intel) Address bit 6 (Motorola) / Address/Data bit 6 (Intel) Address bit 7 (Motorola) / Address/Data bit 7 (Intel) Address bit 8 (Motorola) / Address/Data bit 8 (Intel) Address bit 9 (Motorola) / Address/Data bit 9 (Intel) Address bit 10 (Motorola) / Address/Data bit 10 (Intel) Address bit 11 (Motorola) / Address/Data bit 11 (Intel) Address bit 12 (Motorola) / Address/Data bit 12 (Intel) Address bit 13 (Motorola) / Address/Data bit 13 (Intel) Address bit14 (Motorola) / Address/Data bit 14 (Intel) Address bit15 (Motorola) / Address/Data bit 15 (Intel) Address bit16 (Motorola) / Address bit 16 (Intel) Address bit17 (Motorola) / Address bit 17 (Intel) Address bit18 (Motorola) / Address bit 18 (Intel) Address bit19 (Motorola) / Address bit 19 (Intel) Address bit 20 from P (input) / Address bit 15 for SRAM (output) Address bit 21 from P (input) / Address bit 16 for SRAM (output) Address bit 22 from P (input) / Address bit 17 for SRAM (output) Address bit 23 from P (input) / Address bit 18 for SRAM (output) Data bit 0 for P if not multiplexed (see Note 1). Data bit 1 for P if not multiplexed Data bit 2 for P if not multiplexed Data bit 3 for P if not multiplexed Data bit 4 for P if not multiplexed Data bit 5 for P if not multiplexed Data bit 6 for P if not multiplexed Data bit 7 for P if not multiplexed Data bit 8 for P if not multiplexed
I3 = I1 + Hysteresis ; I4 = I3 + Pull-up ; O8 = Output CMOS 8mA, "1" and "0" at Low Impedance ; O8DT = Output CMOS 8mA, Open Drain or Tristate ;
MICROPROCESSOR INTERFACE (continued)
Type : I1 = Input TTL ; I2 = I1 + Pull-up ; O4 = Output CMOS 4mA ; O4T = O4 + Tristate ; O8D = Output CMOS 8mA, Open Drain ; O8T = Output CMOS 8mA, Tristate
11/101
STLC5465B
I - PIN INFORMATION (continued) I.2 - Pin Description (continued)
Pin N Symbol Type Data bit 9 for P if not multiplexed Data bit 10 for P if not multiplexed Data bit 11 for P if not multiplexed Data bit 12 for P if not multiplexed Data bit 13 for P if not multiplexed Data bit 14 for P if not multiplexed Data bit 15 for P if not multiplexed Function MICROPROCESSOR INTERFACE (continued) 100 101 102 103 104 105 106 D9 D10 D11 D12 D13 D14 D15 I/O I/O I/O I/O I/O I/O I/O
MEMORY INTERFACE 109 110 111 112 113 114 115 116 117 118 119 120 123 124 125 126 127 128 129 130 131 132 135 136 137 138 139 TRI TRO NWE NOE NRAS0/NCE0 NCAS0/NCE1 NRAS1/NCE2 NCAS1/NCE3 NRAS2/NCE4 NCE5 NRAS3/NCE6 NCE7 ADM0 ADM1 ADM2 ADM3 ADM4 ADM5 ADM6 ADM7 ADM8 ADM9 ADM10 ADM11 ADM12 ADM13 ADM14 I3 O4 O4T O4T O4T O4T O4T O4T O4T O4T O4T O4T O8T O8T O8T O8T O8T O8T O8T O8T O8T O8T O8T O8T O8T O8T O8T Token Ring Input (for use Multi-HDLCs in cascade) Token Ring Output (for use Multi-HDLCs in cascade) Write Enable for memory circuits Control Output Enable for memory circuits Row Address Strobe Bank 0 / Chip Enable 0 for SRAM Column Address Strobe Bank 0 / Chip Enable1 for SRAM Row Address Strobe Bank 1 / Chip Enable 2 for SRAM Column Address Strobe Bank 1 / Chip Enable 3 for SRAM Row Address Strobe Bank 2 / Chip Enable 4 for SRAM Chip Enable 5 for SRAM Row Address Strobe Bank 3 / Chip Enable 6 for SRAM Chip Enable 7 for SRAM Address bit 0 for SRAM and DRAM Address bit 1 for SRAM and DRAM Address bit 2 for SRAM and DRAM Address bit 3 for SRAM and DRAM Address bit 4 for SRAM and DRAM Address bit 5 for SRAM and DRAM Address bit 6 for SRAM and DRAM Address bit 7 for SRAM and DRAM Address bit 8 for SRAM and DRAM Address bit 9 for SRAM and DRAM Address bit 10 for SRAM and DRAM Address bit 11 for SRAM only Address bit 12 for SRAM only Address bit 13 for SRAM only Address bit 14 for SRAM only
I3 = I1 + Hysteresis ; I4 = I3 + Pull-up ; O8 = Output CMOS 8mA, "1" and "0" at Low Impedance ; O8DT = Output CMOS 8mA, Open Drain or Tristate ;
Type : I1 = Input TTL ; I2 = I1 + Pull-up ; O4 = Output CMOS 4mA ; O4T = O4 + Tristate ; O8D = Output CMOS 8mA, Open Drain ; O8T = Output CMOS 8mA, Tristate
12/101
STLC5465B
I - PIN INFORMATION (continued) I.2 - Pin Description (continued)
Pin N Symbol Type Function MEMORY INTERFACE (continued) 140 141 142 143 144 147 148 149 150 151 152 153 154 155 156 157 160 DM0 DM1 DM2 DM3 DM4 DM5 DM6 DM7 DM8 DM9 DM10 DM11 DM12 DM13 DM14 DM15 NTEST I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I2 Memory Data bit 0 Memory Data bit 1 Memory Data bit 2 Memory Data bit 3 Memory Data bit 4 Memory Data bit 5 Memory Data bit 6 Memory Data bit 7 Memory Data bit 8 Memory Data bit 9 Memory Data bit 10 Memory Data bit 11 Memory Data bit 12 Memory Data bit 13 Memory Data bit 14 Memory Data bit 15 Test Control. When this pin is at 0V each output is high impedance except XTAL2 Pin.
I3 = I1 + Hysteresis ; I4 = I3 + Pull-up ; O8 = Output CMOS 8mA, "1" and "0" at Low Impedance ; O8DT = Output CMOS 8mA, Open Drain or Tristate ;
Type : I1 = Input TTL ; I2 = I1 + Pull-up ; O4 = Output CMOS 4mA ; O4T = O4 + Tristate ; O8D = Output CMOS 8mA, Open Drain ; O8T = Output CMOS 8mA, Tristate
Note : D0/15 input/output pins must be connected to one single external pull up resistor if not used.
I.3 - Pin Definition I.3.1 - Input Pin Definition I1 : Input 1 TTL I2 : Input 2 TTL + pull-up I3 : Input 3 TTL + hysteresis I4 : Input 4 TTL + hysteresis +pull-up I.3.2 - Output Pin Definition O4 : Output CMOS 4mA O4T : Output CMOS 4mA, Tristate O8 : Output CMOS 8mA O8T : Output CMOS 8mA,Tristate O8D : Output CMOS 8mA,Open Drain O8DT : Output CMOS 8mA,Open Drain or Tristate (Programmable pin) Moreover, each output is high impedance when the NTEST Pin is at 0 volt except XTAL2 Pin which is a CMOS output. I.3.3 - Input/Output Pin Definition I/O : Input TTL/ Output CMOS 8mA. N.B. XTAL1 : this input is CMOS. XTAL2 : NTEST pin at 0 has no effect on this pin.
13/101
STLC5465B
II - BLOCK DIAGRAM The top level functionalities of Multi-HDLC appear on the general block diagram. Figure 1 : General Block Diagram
18 FSCV* 17 FSCG DCLK 49 INT0 16 FS 50 INT1 CB EC RAM Bus RAM INTERFACE 16 Tx MON 32 Tx DMAC INTERRUPT CONTROLLER 16 Rx C/I 32 Rx DMAC 3 XTAL2 4 WATCHDOG XTAL P Bus WDO P INTERFACE Internal Bus BUS ARBITRATION 16 Rx MON 16 Tx C/I
9
5
6
38 12 10 13
CLOCK SELECTION
To Internal Circuit
36
GCI0
39
31 32 33
TIME SLOT ASSIGNER FOR MULTIHDLC
0 1 2 3 4 5 6 7
0 1 2 3 4 5 6
7
20
D7
GCI CHANNEL DEFINITION
SWITCHING MATRIX n x 64 kb/s
Pseudo Random Sequence Analyser
Pseudo Random Sequence Generator
25 24
23 22 21
GCI1
GCI0
DIN6 26
DIN7 27
DIN8 28
7
COUNTER
8
There are : - The switching matrix, - The time slot assigner, - The 32 HDLC transmitters with associated DMA controllers, - The 32 HDLC receivers with associated DMA controllers, - The 16 Command/Indicate and Monitor Channel transmitters belonging to two General Component Interfaces (GCI),
- The 16 Command/Indicate and Monitor Channel receivers belonging to two General Component Interfaces (GCI), - The memory interface, - The microprocessor interface, - The bus arbitration, - The clock selection and time synchronization function, - The interrupt controller, - The watchdog, - The boundary scan.
14/101
VCX OUT
VCX IN
XTAL1
2
32 Rx HDLC with Adress Recognition
V10
32 Tx HDLC with CSMA CR for Content. Bus
34
35
Rx C/I
Rx Tx Rx MON DMAC DMAC
37
GCI1
V10
STLC5465
11
CLOCKB FRAME B CLOCKA FRAME A DOUT7 DOUT6 DOUT5 DOUT4 DOUT3 DOUT2 DOUT1 DOUT0 NDIS DIN0 DIN1 DIN2 DIN3 DIN4 DIN5
STLC5465B
III - FUNCTIONAL DESCRIPTION III.1 - The Switching Matrix N x 64 KBits/S III.1.1 - Function Description The matrix performs a non-blocking switch of 256 time slots from 8 Input Time Division Multiplex (TDM) at 2 Mbit/s to 8 output Time Division Multiplex. A TDM is composed of 32 Time Slots (TS) at 64 kbit/s. The matrix is designed to switch a 64 kbit/s channel (Variable delay mode) or an hyperchannel of data (Sequence integrity mode). So, it will both provide minimum throughput switching delay for voice applications and time slot sequence integrity for data applications on a per channel basis. The requirements of the Sequence Integrity (n*64 kbit/s) mode are the following: All the time slots of a given input frame must be put out during a same output frame. The time slots of an hyperchannel (concatenation of TS in the same TDM) are not crossed together at output in different frames. In variable delay mode, the time slot is put out as soon as possible. (The delay is two or three time slots minimum between input and output). For test facilities, any time slot of an Output TDM (OTDM) can be internally looped back into the same Input TDM number (ITDM) at the same time slot number. A Pseudo Random Sequence Generator and a Pseudo Random Sequence Analyzer are implemented in the matrix. They allow the generation a sequence on a channel or on a hyperchannel, to analyse it and verify its integrity after several switching in the matrix or some passing of the sequence across different boards. The Frame Signal (FS) synchronises ITDM and OTDM but a programmable delay or advance can be introducedseparatelyon each ITDM and OTDM (a half bit time, a bit time or two bit times). An additional pin (PSS) permits the generation of a programmable signal composed of 256 bits per frame at a bit rate of 2048 kbit/s. An external pin (NDIS) asserts a high impedance on all the TDM outputs of the matrix when active (during the initialization of the board for example). III.1.2 - Architecture of the Matrix The matrix is essentially composed of buffer data memories and a connection memory. The received serial datais first converted to parallel by a serial to parallelconverterand stored consecutively in a 256 position Buffer Data Memory (see Figure 2 on Page 16). To satisfy the Sequence Integrity (n*64 kbit/s) requirements, the data memory is built with an even memory, an odd memory and an output memory. Two consecutive frames are stored alternatively in the odd and even memory. During the time an input frame is stored, the one previously stored is transferred into the output memory according to the connectionmemoryswitching orders. A frame later, the output memory is read and data is converted to serial and transferred to the output TDM. III.1.3 - Connection Function Two types of connections are offered : - unidirectional connection and - bidirectional connection. An unidirectional connection makes only the switch of an inputtime slot through an output one whereas a bidirectionalconnectionestablishes the link in the other direction too. So a double connection can be achieved by a single command (see Figure 3 on Page 17). III.1.4 - Loop Back Function Any time slot of an Output TDM can be internally looped back on the time slot which has the same TDM number and the same TS number (OTDMi, TSj) ----> (ITDMi, TSj). In the case of a bidirectional connection, only the one specified by the microprocessor is concerned by the loop back (see Figure 4 on Page 17).
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III - FUNCTIONAL DESCRIPTION (continued) Figure 2 : Switching Matrix Data Path
PRSG : Pseudo Random Sequence Generator PRSA : Pseudo Random Sequence Analyzer OTSV : Output Time Slot Validated INS : Insert CM : Connection Memory (from CMAR Register) BIT SYNCHRO Tx HDLC HDLCM D7 DIN' 7 DIN 0/7 D4/5 1 Rx GCI ME : Message Enable IMTD : Increased Min Throughtput Delay SGV : Sequence Generator Validated SAV : Sequence Analyzer Validated From SMCR Register
DIN 0/7
PRSG
SGV 1
LOOP
1
S/ P
PSEUDO RANDOM SEQUENCE GENERATOR 211 - 1 Rec. O.152
CM (when Read) Internal Bus CONNECTION MEMORY D D Sequence Integrity, LOOP, PRSA, PRSG, INS, OTSV A
D
IMTD
DATA MEMORIES 64kb/s and n x 64kb/s
D
1 A
CMDR Data Register
Sequence Integrity
CM
1 CMAR
INS
1
PRSG
PRSA
SAV
Address Register
ME
1
P/S Tx GCI GCIR D0/7 D4/5 D7 1 Rx HDLC
PSEUDO RANDOM SEQUENCE ANALYZER 211 - 1 Rec. O.152
SFCR R Sequence Fault Counter Register
BIT SYNCHRO
From Connection Memory OTSV (per channel)
OR
From OMCR Register OMV (per multiplex) From N DIS PIN (for all multiplexes)
DOUT 0/7
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STLC5465B
III - FUNCTIONAL DESCRIPTION (continued) Figure 3 : Unidirectional and Bidirectional Connections
OTSy, OTDMq DOWN STREAM
DATA MEMORY n x 64kb/s Unidirectional Connection
ITSx,ITDMp DOWN STREAM
OTSy, OTDMq DOWN STREAM ITSy, ITDMq UP STREAM
DATA MEMORY n x 64kb/s
ITSx,ITDMp DOWN STREAM OTSx, OTDMp
5464-04.EPS
DATA MEMORY n x 64kb/s Bidirectional Connection
UP STREAM p, q = 0 to 7 x, y = 0 to 31
Figure 4 : Loop Back
OTSV OTSy, OTDMq DOWN STREAM
DATA MEMORY n x 64kb/s
ITSx,ITDMp DOWN STREAM OTSx, OTDMp UP STREAM p, q = 0 to 7 x, y = 0 to 31
5464-05.EPS
ITSy, ITDMq UP STREAM
DATA MEMORY n x 64kb/s
Loop Loopback per channel relevant if bidirectional connection has been done.
III.1.5 - Delay through the Matrix III.1.5.1 - Variable Delay Mode In the variable delay mode, the delay through the matrixdepends on the relative positions of the input and output time slots in the frame. So, some limits are fixed : - the maximum delay is a frame + 2 time slots, - the minimum delay is programmable. Three time slots if IMTD = 1, in this case n = 2 in the formula hereafter or two time slots if IMTD = 0, in this case n = 1 in the same formula (see Paragraph "Switching Matrix Configuration Reg SMCR (0C)H" on Page 64). All the possibilities can be ranked in three cases : a) If OTSy > ITSx + n then the variable delay is : OTSy - ITSx Time slots
b) If ITSx < OTSy < ITSx + n then the variable delay is : OTSy - ITSx + 32 Time slots c) OTSy < ITSx then the variable delay is : 32 - (ITSx - OTSy) Time slots. N.B. Rule b) and rule c) are identical. For n = 1 and n = 2, see Figure 5 on Page 18. III.1.5.2 - Sequence Integrity Mode In the sequence integrity mode (SI = 1, bit located in the ConnectionMemory), the input time slots are put out 2 frames later (fig. 6 - page19). In this case, the delay is defined by a single expression : Constant Delay = (32 - ITSx) + 32 + OTSy So, the delay in sequence integrity mode varies from 33 to 95 time slots.
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III - FUNCTIONAL DESCRIPTION (continued) Figure 5 : Variable Delay through the matrix with ITDM = 1
1) Cas e : If OTS y > ITS x + 2, th en Va ria ble De lay is : OTS y - ITS x Time S lots Fra me n Inp ut F ra me ITS 0 ITSx ITSx+1 ITS x+2 ITS31 ITS 0 F ra me n + 1 ITS31
y>x+2 Ou tpu t F ra me OTS 0 Variable De lay (OTS y - ITSx) OTS y OTS 31
2) Cas e : If ITSx OTS y ITS x + 2, the n Varia ble De lay is : OTS y - ITSx + 32 Time S lots Fra me n F ra me n + 1 Inp ut F ra me ITS 0 ITSx ITSx+1 ITS x+2 ITS31 ITS 0 ITSx ITS31
xyx+2 Ou tpu t F ra me OTS 0 OTS y 32 Time S lots OTS y OTS 31
Variable De lay : OTS y - ITS x + 32 Time S lots
3) Cas e : If OTS y < ITS x, th en Varia ble De la y is : 32 - (ITS x - OTS y) Tim eS lots Fra me n Inp ut F ra me ITS 0 ITSx ITS31 ITS 0
F ra me n + 1 ITSx ITS31
y5464-06.EPS
OTS 31
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III - FUNCTIONAL DESCRIPTION (continued) Figure 6: Variable Delay through the matrix with ITDM = 0
1) Case : If OTSy > ITSx + 1, then Variable Delay is : OTSy - ITSx TimeSlots Frame n Input Frame
Frame n + 1 ITS31
ITS0
ITSx ITSx+1 ITSx+2
ITS31 ITS0
y>x+1
Output Frame
OTS0 Variable Delay (OTSy - ITSx) OTSy
OTS31
2) Case : If ITSx OTSy ITSx + 1, then Variable Delay is : OTSy - ITSx + 32 TimeSlots Frame n Frame n + 1 Input Frame
ITS0
ITSx ITSx+1 ITSx+2
ITS31 ITS0
ITSx
ITS31
xyx+1
Output Frame
OTS0 OTSy 32 TimeSlots OTSy
OTS31
Variable Delay : OTSy - ITSx + 32 TimeSlots
3) Case : If OTSy < ITSx, then Variable Delay is : 32 - (ITSx - OTSy) TimeSlots Frame n Input Frame
Frame n + 1 ITSx ITS31
ITS0
ITSx
ITS31 ITS0
yOutput Frame
OTS0 OTSy Variable Delay : 32 - (ITSx - OTSy) TimeSlots 32 TimeSlots OTSy
OTS31
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III - FUNCTIONAL DESCRIPTION (continued) Figure 7 : Constant Delay through the matrix with SI = 1
Con s tan t Delay = (32 -ITSx) + 32 + OTS y
ITS : Input TimeS lot OTS : Output Time S lot 0 x 31 0 y 31
Frame n
Frame n + 1
Frame n + 2
ITS0
ITS31
ITS0
ITS31
ITS0
ITS31
Min. Cons tant Delay = 33TS 1 + 32 Time S lots
OTS 0 +0
OTS 31 = 33 Time S lots
Max. Cons tant Delay = 95 Time S lots 32 - 0 + 32 + 31
OTS 31 = 95 Time S lots = Cons tant Delay
5464-08.EPS
(32 - ITSx)
+ 32
+ OTSy
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III - FUNCTIONAL DESCRIPTION (continued) III.1.6 - Connection Memory III.1.6.1 - Description The connection memory is composed of 256 locations addressed by the number of OTDM and TS (8x32). Each location permits : - to connect each input time slot to one output time slot (If two or more output time slots are connected to the same input time slot number, there is broadcasting). - to selectthe variable delay mode or the sequence integrity mode for any time slot. - to loop back an output time slot. In this case the contents of an input time slot (ITSx, ITDMp) is the same as the output time slot (OTSx,OTDMp). - to output the contents of the corresponding connection memory instead of the data which has been stored in data memory. - to output the sequence of the pseudo random sequence generator on an output time slot: a pseudo random sequence can be inserted in one or several time slots (hyperchannel) of the same Output TDM ; this insertion must be enabled by the microprocessor in the configuration register of the matrix. - to define the source of a sequenceby the pseudo random sequence analyzer: a pseudo random sequence can be extracted from one or several time slots (hyperchannel) of the same Input TDM and routed to the analyzer; this extraction can be enabled by the microprocessor in the configuration register of the matrix (SMCR). - to assert a high impedance level on an output time slot (disconnection). - to deliver a programmable 256-bit sequence during 125 microseconds on the Programmablesynchronization Signal pin (PSS). III.1.6.2 - Access to Connection Memory Supposing that the Switching Matrix Configuration Register (SMCR) has been already written by the microprocessor, it is possible to access to the connection memory from microprocessor with the help of two registers : - Connection Memory Data Register (CMDR) and - Connection Memory Address Register (CMAR). III.1.6.3 - Access to Data Memory To extract the contents of the data memory it is possible to read the data memory from microprocessor with the help of the two registers : - Connection Memory Data Register (CMDR) and - Connection Memory Address Register (CMAR).
III.1.6.4 - Switching at 32 Kbit/s Four TDMs can be programmed individually to carry 64 channels at 32 Kbit/s (only if these TDMs are at 2 Mbit/s). Two bits (SW0/1) located in SMCR define the type of channels of two couples of TDMs. SW0 defines TDM0 and TDM4 (GCI0) and SW1 defines TDM1 and TDM5 (GCI1). If TDM0 or/and TDM1 carry 64 channels at 32 Kbit/s then TDM2 or/and TDM3 are not available externally they are used internally to perform the function. Downstream switching at 32 kb/s on page 22. Upstream switching at 32 kb/s on page 23.
III.1.6.5 - Switching at 16 kbit/s The TDM4 and TDM5 can be GCI multipexes.Each GCI multipex comprises 8 GCI channels. Each GCI channel comprises one D channelat 16 Kbit/s. See GCI channel definition GCI Synchro signal delivered by the Multi-HDLC on page 30. It ispossibleto switch the contents of 16 D channels from the 16 GCI channels to 4 timeslots of the 256 output timeslots. In the other direction the contents of an selected timeslot is automatically switched to 4 D channels at 16 Kbit/s. See Connection Memory Data Register CMDR (0E)H on page 74
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III - FUNCTIONAL DESCRIPTION (continued) Figure 8: Downstream Switching at 32kb/s
3.9s a DIN0 a din2 c dout2 d dout4 Internal command If SW0=1 DOUT4 (GCI 0) D d C/I A E c b a b MON D C/I a b c d e b Free c Free d Free e
B1
B2
MON
D
C/I
DOUT 4 (GCI 0) DOUT2
dout 4 dout 2 Internal commands dout 5 dout 3
din 0 din 2
DIN0 4 bit shifting SW0=1 Switching at 32 kb/ s DIN2 not use d
DOUT 5 (GCI 1) DOUT3
din 1 din 3 SW1=1
DIN 1
4 bit shifting DIN3 not used
MULTI HDLC STLC 546 5
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III - FUNCTIONAL DESCRIPTION (continued) Figure 9: Upstream Switching at 32kb/s
Timeslot (3.9s) DIN4 (GCI 0) d c b a
B1 DOUT6 B2 GCI 1 DIN6 = shifted DOUT6 B2 GCI1 d c b
B2 a x
MON y
D C/I z B2 GCI 1 y
B1 GCI 0 d
B2 GCI 0
B1 GCI 1 a x
c
b
B1 GCI 0 Free
B2 GCI 0
B1 GCI1 Free e
a
DOUT0
Free
b
c
Free
d
DOUT 0 Internal loopback and 4 bit shifting (2+2) by software
DIN4
GCI 0
From DOUT6
DOUT6 Switching at 32 kb/s DOUT1
DIN6
DIN5
GCI1
MULTI HDLC
STLC 5465
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III - FUNCTIONAL DESCRIPTION (continued) Figure 10: Upstream and Downstream Switching at 16kb/s
TDM side
D11 D12 D21 D22 D31 D32 D41 D42
GCI side
D11 D12 C1 C2 C3 C4 A E
TSy
TS 16n+3
TSy of any TDM can be programmable with y comprised between 0 and . 31
D21 D22 C1 C2 C3 C4 A E
TS 16n+7
D31 D32 C1 C2 C3 C4 A E
TS 16n+11
D41 D42 C1 C2 C3 C4 A E
TS 16n+15
n: GCI channel number, 0 to 1
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III - FUNCTIONAL DESCRIPTION (continued) III.2 - HDLC Controller III.2.1 - Function Description The internal HDLC controller can run up to 32 channels in a conventional HDLC mode or in a transparent (non-HDLC) mode (configurable per channel). Each channel bit rate is programmablefrom 4kbit/s to 64kbit/s. All the configurations are also possible from 32 channels (from 4 to 64 kbit/s) to one channel at 2 Mbit/s. In reception,the HDLC time slots can directly come from the input TDM DIN8 (direct HDLC Input) or from any other TDM input after switching towards the output 7 of the matrix (configurable per time slot). In transmission, the HDLC frames are sent on the output DOUT6 and on the output CB (with or without contention mechanism), or are switched towards the other TDM output via the input 7 of the matrix (see Figure 11). III.2.1.1 - Format of the HDLC Frame The format of anHDLCframe is thesame in receive and transmit direction and shown here after. Figure 11 : HDLC and DMA Controller Block Diagram
DOUT 6 Dire ct HDLC Output From Output 7 of the Matrix From Output 6 of the Matrix DIN 8 Dire ct HDLC Input To Input 7 of the Matrix TIME SLOT ASSIGNER Conte ntion Bus
III.2.1.2 - Composition of an HDLC Frame
Opening Flag Address Field (first byte) Address Field (second byte) Command Field (first byte) Command Field (second byte) Data (first byte) Data (optional) Data (last byte) FCS (first byte) FCS (second byte) Closing Flag
- Opening Flag - One or two bytes for address recognition (reception) and insertion (transmission) - Data bytes with bit stuffing - Frame Check Sequence: CRC with polynomial G(x) = x16 +x12+x5+1 - Closing Flag.
32 Rx HDLC
32 CSMA-CR
Echo
32 ADDRESS RECOGNITION
32 Tx HDLC
32 Rx FIFO's
32 Tx FIFO's
32 Rx DMAC
32 Rx DMAC
P INTERFACE
RAM INTERFACE
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III - FUNCTIONAL DESCRIPTION (continued) III.2.1.3 - Description and Functions of the HDLC Bytes - FLAG The binary sequence 01111110marks the beginning and the end of the HDLC Frame. Note : In reception, three possible flag configurations are allowed and correctly detected : - two normal consecutive flags : ...0111111001111110... - two consecutive flags with a "0" common : ...011111101111110... - a global common flag : ...01111110... this flag is the closing flag for the current frame and the opening flag for the next frame - ABORT The binary sequence 1111111 marks an Abort command. In reception,seven consecutive1's, insidea message, are detected as an abort command and generates an interrupt to the host. In transmit direction, an abort is sent upon command of the micro-processor. No ending flag is expected after the abort command. - BIT STUFFING AND UNSTUFFING This operation is done to avoid the confusion of a data byte with a flag. In transmission, if five consecutive 1's appear in the serial stream being transmitted,a zerois automatically inserted (bit stuffing) after he fifth "1". In reception, if five consecutive "1" followed by a zero are received, the "0" is assumed to have been inserted and is automatically deleted (bit unstuffing). - FRAME CHECK SEQUENCE TheFrameCheck Sequenceiscalculatedaccording to the recommendationQ921 of the CCITT. - ADDRESS RECOGNITION In the frame, one or two bytes are transmitted to indicate the destination of the message. Two types of addresses are possible : - a specific destination address - a broadcast address. In reception, the controller compares the receive addresses to internal registers, which contain its own address. 4 bits in the receive command register (HRCR) inform the receiver of which registers, it has to take into account for the comparison. The receiver can compare one or two address bytes of the message to the specific board address and/or the broadcast address. For the specific destination address only, the receiver can compare or not each bit of the two receive address bytes to the programmable Address Field Recognition register. An Address
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Field Recognition Mask register is associated to each Address Field Recognition register; so each received address bit can be masked or not individually. The programmableAddressField Recognitionregister is located in the Address Field Recognition MemoryandtheprogrammableAddressField Recognition Mask register is located in the Address Field Recognition Mask Memory. Upon an address match, the address and the data followingare writtento the databuffers; upon an address mismatch, the frame is ignored. So, it authorizes the filtering of the messages. If no comparison is specified, each frame is received whatever its address field. In Transmission, the whole of the transmit frame is located in shared memory; the controllersends the frame including the destination or broadcast addresses. III.2.2 - CSMA/CR Capability An HDLC channel can come in and go out by any TDM input on the matrix. For time constraints, direct HDLC Access is achieved by the input TDM (DIN 8) and the output TDM (DOUT6). In transmission, a time slot of a TDM can be shared between different sources in Multi-point to point configuration(differentsubscriber'sboardsforexample). The arbitration system is the CSMA/CR(Carrier Sense Multiple access with ContentionResolution). The contention is resolved by a bus connected to the CB pin (Contention Bus). This bus is a 2Mbit/s wire line common to all the potential sources. If a Multi-HDLC has obtained the access to the bus, the data to transmit is sent simultaneouslyon the CB line and the outputTDM. The result of the contention isreadback ontheEcholine. If a collision is detected, the transmission is stopped immediately. A contention on a bit basis is so achieved. Each message to be sent with CSMA/CR has a priority class (PRI = 8, 10) indicated by the Transmit Descriptor and some rules are implemented to arbitrate the access to the line. The CSMA/CR Algorithm is given. When a request to send a message occurs, the transmitter determines if the shared channel is free. The MultiHDLClistensto theEcholine.If C or more consecutive "1" are detected (C depending on the message's priority), the Multi-HDLC begins to send its message. Each bit sent is sampled back and compared with the original value to send. If a bit is different, the transmission is instantaneouslystopped(beforethe end of this bit time) andwill restart as soon asthe Multi-HDLC will detectthatthe channel is free withoutinterruptingthe microprocessor. After a successful transmission of a message, a
STLC5465B
III - FUNCTIONAL DESCRIPTION (continued) programmable penalty PEN(1 or 2) is applied to the transmitter (see Paragraph HDLC Transmit Command Register on Page 81). It guarantees that the same transmitter will not take the bus another time before a transmitter which has to send a message of same priority. In case of a collision, the frame which has been aborted is automatically retransmitted by the DMA controller without warning the microprocessor of this collision. The frame can be located in several buffers in external memory. The collision can be detected from the second bit of the opening frame to the last but one bit of the closing frame. III.2.3 - Time Slot Assigner Memory Each HDLC channel is bidirectional and configurate by the Time Slot Assigner (TSA). The TSAis a memoryof 32 words (one per physical Time Slot) where all of the 32 input and output time slots of the HDLC controllers can be associated to logical HDLC channels. Super channels are created by assigning the same logical channel number to several physical time slots. The following features are configurate for each HDLC time slot : - Time slot used or not - One logical channel number - Its source : (DIN 8 or the output 7 of the matrix) - Its bit rate and concerned bits (4kbit/s to 64kbit/s). 4kbit/s correspond to one bit transmitted each two frames. This bit must be present in two consecutive frames in reception, and repeated twice in transmission. - Its destination : - direct output on DOUT6 - direct output on DOUT6 and on the Contention Bus (CB) - on another OTDM via input 7 of the matrix and on the Contention Bus (CB) III.2.4 - Data Storage Structure Data associated with each Rx and Tx HDLC channel is stored in externalmemory; The data transfers between the HDLC controllers and memory are ensured by 32 DMAC (Direct MemoryAccess Controller) in reception and 32 DMAC in transmission. The storage structure chosen in both directions is composed of one circular queue of buffers per channel. In such a queue, each data buffer is pointed to by a Descriptor located in external memory too. The main information contained in the Descriptor is the address of the Data Buffer, its length and the address of the next Descriptor; so the descriptors can be linked together. This structure allows to : - Store receive frames of variable and unknown length - Read transmit frames stored in external memory by the host - Easily perform the frame relay function. III.2.4.1 - Reception At the initialization of the application, the host has to prepare an Initialization Block memory, which contains the first receive buffer descriptor address for each channel, and the receive circular queues. At the opening of a receive channel, the DMA controller reads the address of the first buffer descriptor corresponding to this channel in the initialization Block. Then, the data transfer can occur without intervention of the processor (see Figure 12 on Page 28). A new HDLC frame always begins in a new buffer. A long frame can be split between several buffers if the buffer size is not sufficient. All the information concerning the frame and its location in the circular queue is included in the Receive Buffer Descriptor : - The Receive Buffer Address (RBA), - The size of the receive buffer (SOB), - The number of bytes written into the buffer(NBR), - The Next Receive Descriptor Address (NRDA), - The status concerning the receive frame, - The control of the queue. III.2.4.2 - Transmission In transmission, the data is managed by a similar structure as in reception (see Figure 13 on Page 28). By the same way, a frame can be split up between consecutive transmit buffers. The main information contained in the Transmit Descriptor are : - transmit buffer address (TBA), - number of bytes to transmit (NBT) concerningthe buffer, - next transmit descriptor address (NTDA), - status of the frame after transmission, - control bit of the queue, - CSMA/CR priority (8 or 10). III.2.4.3 - Frame Relay The principle of the frame relay is to transmit a frame which has been received without treatment. A new heading is just added. This will be easily achieved, taking into account that the queue structure allows the transmission of a frame split between several buffers.
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III - FUNCTIONAL DESCRIPTION (continued) Figure 12 : Structure of the Receive Circular Queue
Initialization Block up to 32 channels 0 1 RDA RDA RECEIVE DMA CONTROLLER
31
RDA Receive Descriptor 2
Initial Receive Descriptor
NRDA RBA
NRDA RBA
Receive Buffer 1 Receive Descriptor n NRDA RBA
Receive Buffer 2
Receive Descriptor 3 NRDA RBA Receive Buffer n Receive Buffer 3 One receive circular queue by channel
Figure 13 : Structure of the Transmit Circular Queue
Initialization Block up to 32 channels 0 1 TDA TDA TRANSMIT DMA CONTROLLER
31
TDA Transmit Descriptor 2 NTDA TBA
Initial Transmit Descriptor NTDA TBA
Transmit Buffer 1 Transmit Descriptor n NTDA TBA
Transmit Buffer 2
Transmit Descriptor 3 NTDA TBA Transmit Buffer n Transmit Buffer 3 One transmit circular queue by channel
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III - FUNCTIONAL DESCRIPTION (continued) III.2.5 - Transparent Modes In the transparentmode, the Multi-HDLC transmits data in a completely transparent manner without performing any bit manipulation or Flag insertion. The transparent mode is per byte function. Two transparent modes are offered : - First mode : for the receive channels, the Multi-HDLC continuously writes received bytes into the external memory as specified in the current receive descriptorwithout taking into account the Fill Character Register. - Secondmode : the Fill CharacterRegister specifies the "fill character" which must be takeninto account. In reception, the"fill character" will notbe transferred totheexternalmemory. Thedetectionof"Fill character" marks the end of a message and generates an interruptif BINT=1(seeTransmit DescriptoronPage 95). When the "Fill character" is not detected a new message is receiving. As for the HDLC mode the correspondence between the physical time slot and the logical channel is fully defined in the Time Slot Assigner memory (Time slot used or not used, logical channel number, source, destination). III.2.6 - Command of the HDLC Channels The microprocessor is able to control each HDLC receive and transmit channel. Some of the commands are specific to the transmission or the reception but others are identical. III.2.6.1 - Reception Control The configuration of the controller operating mode is: HDLC mode or Transparent mode. The control of the controller: START, HALT, CONTINUE, ABORT. - START : On a start command, the RxDMA controller reads the address of the first descriptor in the initialization block memory and is ready to receive a frame. - HALT : For overloading reasons, the microprocessor can decide to halt the reception. The DMA controller finishes transfer of the current frame to external memory and stops. The channel can be restarted on CONTINUE command. - CONTINUE : The reception restarts in the next descriptor. - ABORT: On an abort command, the reception is instantaneously stopped. The channel can be restarted on a START or CONTINUE command. Reception of FLAG (01111110) or IDLE (11111111) between Frames. Address recognition. The microprocessor defines the addressesthat the Rx controllerhas to take into account. In transparent mode: "fill character" register selected or not. III.2.6.2 - Transmission Control The configuration of the controller operating mode is : HDLC mode or Transparent mode. The control of the controller : START, HALT, CONTINUE, ABORT. - START : On a start command, the Tx DMAcontroller reads the address of the first descriptor in the initialization block memory and tries to transmit the first frame if End Of Queue is not at "1". - HALT : The transmitter finishes to send the current frame and stops.Thechannel can be restarted on a CONTINUE command. - CONTINUE : if the CONTINUE command occurs after HALT command, the HDLC Transmitter restarts by transmitting the next buffer associated to the next descriptor. If the CONTINUE command occurs after an ABORT command which has occurred during a frame, the HDLC transmitter restarts by transmitting the frame which has been effectivelyaborted by the microprocessor. - ABORT: On an abort command, the transmission of the current frame is instantaneously stopped, an ABORT sequence "1111111" is sent, followed by IDLE or FLAG bytes. The channel can be restarted on a START or CONTINUE command. Transmission of FLAG (01111110) or IDLE (111111111) between frames can be selected. CRC can be generated or not. If the CRC is not generated by the HDLC Controller, it must be located in the shared memory. In transparent mode: "fill character" register can be selected or not. III.3 - C/I and Monitor III.3.1 - Function Description The Multi-HDLC is able to operate both GCI and V* links. The TDM DIN/DOUT 4 and 5 are internally connected to the CI and Monitor receivers/transmitters. Since the controllershandleup to 16 CI and 16 Monitor channels simultaneously, the MultiHDLC can manage up to 16 level 1 circuits. The Multi-HDLC can be used to support the CI and monitor channels based on the following protocols : - ISDN V* protocol - ISDN GCI protocol - Analog GCI protocol.
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III - FUNCTIONAL DESCRIPTION (continued) III.3.2 - GCI and V* Protocol A TDM can carry 8 GCI channels or V* channels. The monitor and S/C bytes always stand at the same position in the TDM in both cases.
Channel 0 TS0 B1 TS1 B2 TS2 MON TS3 S/C Channel 1 to Channel 30 TS28 B1 Channel 31 TS29 B2 TS30 MON TS31 S/C
The GCI or V* channels are composed of 4 bytes and have both the same general structure.
B1 B2 MON S/C
III.3.3 - Structure of the Treatment GCI/V* TDM's are connected to DIN 4 and DIN 5. The D channels are switched through the matrix towards the output 7 and the HDLC receiver. The Monitor and S/C bytes are multiplexed and sent to the CI and Monitor receivers (see Figure 14 on Page 31). In transmission, the S/C and Monitor bytes are recombined by multiplexing the information provided by the Monitor,C/I and theHDLC Transmitter. Like in reception,the D channelis switchedthrough the matrix. III.3.4 - CI and Monitor Channel Configuration
B1, B2 : Bytes of data. Those bytes are not affectedby the monitor and CI protocols. MON : Monitor channel for operation and maintenance information. S/C : Signalling and control information. Only Monitor handshakes and S/C bytes are different in the three protocols : ISDN V* S/C byte
D C/I 4 bits T E
ISDN GCI S/C byte
D C/I 4 bits A E
Analog GCI S/C byte
C/I 6 bits A E
Monitor channel data is located in a time slot ; the CI and monitor handshake bits are in the next time slot. Each channel can be defined independently. A table with all the possible configurations is presented hereafter (Table 13). Table 13 : C/I and MON Channel Configuration
C/I validated or not Monitor validated or not CI For analog subscriber (6 bits) CI For ISDN subscriber (4 bits) Monitor V* Monitor GCI
CI : The Command/Indicate channel is used for activation/deactivation of lines and control functions. D : These 2 bits carry the 16 kbit/s ISDN basic access D channel. In GCI protocol, A and E are the handshake bits and are used to control the transfer of information on monitor channels.The E bit indicates the transfer of each new byte in one direction and the A bit acknowledges this byte transfer in the reverse direction. In V* protocol,there isn't any handshakemode.The transmitter has only to mark the validity of the Monitor byte by positioning the E bit (T is not used and is forced to "1"). For more information about the GCI and V*, refer to the General Interface Circuit Specification (issue1.0, march 1989) and the France Telecom Specification about ISDN Basic Access second generation (November 1990).
Note : A mix of V* and GCI monitoring can be performed for two distinct channels in the same application.
III.3.5 - CI and Monitor Transmission/Reception Command The reception of C/I and Monitor messages are managed by two interrupt queues. In transmission, a transmit command register is implemented for each C/I and monitor channel (16 C/I transmit command registers and 16 Monitor transmit command registers). Those registers are accessible in read and write modes by the microprocessor.
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III - FUNCTIONAL DESCRIPTION (continued) Figure 14 : D, C/I and Monitor Channel Path
DIN 5 DIN 4 DOUT 4 DOUT 5
GCI1
GCI0
D Cha nnels from Tx HDLC
0 1 2 3 4 5 6 7
SWITCHING MATRIX
0 1 2 3 4 5 6 7
GCI0
GCI1
D Cha nne ls to Rx HDLC
GCI CHANNEL DEFINITION
16 Rx C/I
16 Rx MON
16 Tx C/I
16 Tx MON
INTER RUPT CONTR OLLER
5464-12.EPS
Inte rnal Bus
III.3.6 - Scrambler and Descrambler The TDM4 and TDM5 canbe GCImultipexes. Each GCI multipex comprises 8 GCI channels.Each GCI channel comprises two B channels at 64 Kbit/s. In reception it is possible to switch and to scramble the contents of 32 B channels of GCI channels to 32 timeslots of the 256 output timeslots. In transmission these 32 timeslots are assigned to 32 B channels. In the other direction the contents of an selected B channels is automatically switched and descrambled to one B channel of 16 GCI channel. See Connection Memory Data Register CMDR (0E)H on page 74 (SCR bit). Connection between "ISDN channels" and GCI channels. Three timeslots are assigned to one"ISDN channels". Each "ISDN channels" comprises three channels:B1+B2+B* with B*= D1,D2, A, E, S1, S2, S3, S4. GCI channel to/from ISDN channel on page 32. Upstream. From GCI channels to ISDN channels on page 33.
- in reception: 16 GCI channels (B1+B2+MON+ D+C/I), - in transmission: 16 ISDN channels (B1+B2+B*). It is possible to switch the contents of B1, B2 and D channelsfrom 16 GCI channelsin any16 "ISDN channels", TDM side. The contents of B1 and/or B2 can be scrambled or not. If scrambledthe number of the32 timeslots (TDM side) are different mandatory. Receiving the contents of Monitor and Command / Indicate channels from 16 GCI channels. Primitives and messages are stored automatically in the external shared memory. Transmitting "six bit word" (A, E, S1, S2, S3, S4) to any 16 "ISDN channels" TDM side or not. See SBV bit of General Configuration Register GCR (02)H on page 68. Downstream. From ISDN channels to GCI channels on page 34. - in reception: ISDN channel (B1+B2+B*) - in transmission: GCI channel (B1+B2+MON+ D+C/I) It is possible to switch the contents of B1, B2 and D channels from 16 "ISDN channels", TDM side
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III - FUNCTIONAL DESCRIPTION (continued) in 16 GCI channels. The contents of B1 and/or B2 can be descrambled or not. If descrambled the 32 B1/B2 belong to GCI channels mandatory. Receiving six bit word (A, E, S1, S2, S3, S4) from any 16 "ISDN channels", TDM side. The 16 "six bit word" are stored automatically in the external shared memory. Transmitting the contents of Monitor and Command / Indicate channels to 16 GCI channels. Figure 15: GCI channel to/from ISDN Channel
TDM side
B1 B1 B1 B1 B1 B1 B1 B1 B1 B2 B2 B2 B2 B2 B2 B2 B2 D D A E S1 S2 S3 S4
See SBV bit of General Configuration Register GCR (02)H on page 68. Alarm Indication Signal. This detection concerns 16 hyperchannels. One hyperchannel comprises 16 bits (B1 and B2 only). The Alarm Indications for the 16 hyperchannelsare stored automatically in the external shared memory. See AISD bit of SwitchingMatrix Configuration Reg SMCR (0C)H on page 71.
GCI side
B1 B1 B1 B1 B1 B1 B1 B1 B1 B2 B2 B2 B2 B2 B2 B2 B2 M1 M2 M3 M4 M5 M6 M7 M8 D D C1 C2 C3 C4 A E
TS3m
SCRAMBLER / DESCRAMBLER
TS4n
TS3m+1
SCRAMBLER / DESCRAMBLER
TS4n+1
TS3m+2
TS4n+2
PCM at 2 Mb/s m: ISDN channel number, 0 to 9 If TDM at 4 Mb/s odd timeslot or even timeslot can be selected
TS4n+3
n: GCI channel number, 0 to 7
Six bit word Primitive Command Indicate controllers RX TX
Monitor controllers TX RX
C/I interrupt Queue located in shared memory
Microprocessor
MON interrupt Queue located in shared memory
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III - FUNCTIONAL DESCRIPTION (continued) Figure 16: From GCI Channels to ISDN Channels
SCRAMBLER up to 32 SCR by timeslot
SBV for the 16 controllers
Extension TX C/I controllers up to 16 for A, E, S1 to S4
TDM 0, 2 if PCM at 4 Mb/s
1 B1, B2 D, A, E S1 to S4 SWITCHING MATRIX
GCI side DIN4/5
RX C/I controllers up to 16 for primitives
RX MON controllers up to 16
Interrupt controller
Microprocessor
C/I interrupt Queue, MON interrupt Queue, located in shared memory
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III - FUNCTIONAL DESCRIPTION (continued) Figure 17: From ISDN channels to GCI Channels
DESCRAMBLE R up to 32 SCR by timeslot
TDM 0, 2 if PCM at 4 Mb/ s
SWITCHING MATRIX
B1, B2 B1, B2
GCI side DOUT4/5
D
B1, B2 (16 bits)
A, E, S1 to S4
C/I
A, E, MON
AIS Extension RX Detection C/I controller up to 16 up to 16 ISDN channels ISDN channels
TX C/I controller up to 16 primitives
TX MON controller up to 16 primitives
Interrupt controller
C/I interrupt Queue located in shared memory
Microprocessor
III.4 - Microprocessor Interface III.4.1 - Description The Multi-HDLC circuit can be controlledby several types of microprocessors (ST9, Intel/Motorola 8 or 16 data bits interfaces) such as : - ST9 family - INTEL 80C188 8 bits - INTEL 80C186 16 bits - MOTOROLA 68000 16 bits - MOTOROLA 68020 16/32 bits - ST10 family During the initialization of the Multi-HDLC circuit, the microprocessor interfaceis informedof thetype of microprocessor that is connectedby polarisation of three external pins MOD 0/2). Two chip Select (CS0/1) pins are provided.CS0 will
select the internal registers and CS1 the external memory. Table 14 : Microprocessor Interface Selection
MOD2 Pin 0 1 1 0 0 1 1 0 MOD1 Pin 1 1 0 0 0 0 1 1 MOD0 Pin 1 1 0 0 1 1 0 0 Microprocessor 80C188 80C186 68000 68020 ST9 ST10 A/D multiplexed ST10 A/D not multiplexed Reserved
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III.4.2 - Exchange with the shared memory A Fetch Buffer located in the microprocessor interface allows to reduce the shared memory access cycle for the microprocessor. It is used whatevermicroprocessorselected thanks to MOD0/2 pins. This Fetch Buffer consists of one Write FIFO and four Read Fetch Memories. III.4.2.1 - Write FIFO When the microprocessor delivers the address word named An to write data named [An] in the shared memory in fact it writes data [An] and addressword An in the Write FIFO (Deep 4 words). If An is in Fetch Memory, [An] is removed in Fetch Memory. The number of wait cycles for the microprocessor is strongly reduced. Figure 17.1: Write FIFO and Fetch Memories. III.4.2.2 - Read Fetch Memory When the microprocessor delivers the address word named An to read data named [An] out of the shared memory in fact it reads data [An] from one of four Read Fetch Memories. The number of wait cycle for the microprocessor is strongly reduced and can reach zero when An, address word delivered by the microprocessor, and data [An] is already in the Read Fetch Memory and validated. The source of [An] is truly the shared memory whatever An. III.4.3 - Definition of the Interface for the different microprocessors The signals connected to the microprocessor interface are presented on the following figures for the different microprocessor.
Shared memory
To shared memory
From shared memory
Write FIFO
An, [An] An+1, [An+1] An+2, [An+2] An+3, [An+3] microprocessor interface
Read Fetch Memory
Four Fetch Memories An, [An]
From microprocessor
To microprocessor
Microprocessor
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III - FUNCTIONAL DESCRIPTION (continued) Figure 18 : Multi-HDLC connected to P with multiplexed buses
MULTI-HDLC
P ST9/10 INTEL MOTOROLA 8/16 BITS Multiplex Address/Data Bus Address Bus P INTERFACE Internal Bus RAM INTERFACE Data Bus BUS ARBITRATION STATIC or DYNAMIC RAM (organized by 16 bits)
Figure 19 : Multi-HDLC connected to P with non-multiplexed buses
MULTI-HDLC
P ST10 INTEL MOTOROLA 8/16 BITS
Address Bus
P INTERFACE
Address Bus Internal Bus RAM INTERFACE Data Bus BUS ARBITRATION
Data Bus
STATIC or DYNAMIC RAM (organized by 16 bits)
Figure 20 : Microprocessor Interface for INTEL 80C188
INT0/1 WDO NRES ET CS 0/1
ARDY
INTEL 80C188
NWR NRD ALE
P INTERFACE
AD0/7
Figure 21 : Microprocessor Interface for INTEL 80C186
INT0/1 WDO NRES ET CS 0/1 NBHE ARDY
INTEL 80C186
NWR NRD ALE
P INTERFACE
AD0/15
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III - FUNCTIONAL DESCRIPTION (continued) Figure 22 : Microprocessor Interface for MOTOROLA 68000
INT0/1 WDO NRES ET CS 0/1 NDTACK R/NW MHDLC
MOTOROLA 68000
NUDS NLDS NAS A1/23 AD8/15 AD0/7 R/NW CS0/1, Ax/23
P INTERFACE
Figure 23 : Microprocessor Interface for MOTOROLA 68020
INT0/1 WDO MHDLC NRESET CS0/1 NDSACK0/1 SIZE0/1
MOTOROLA 68020 0
R/NW NDS NAS A0/23 AD8/15 AD0/7 R/NW CS0/1, Ax/23
P INTERFACE
Figure 24 : Microprocessor Interface for ST9
INT0/1 WDO MHDLC NRES ET CS 0/1
WAIT
S T9
R/NW NDS NAS
P INTERFACE
AD0/7
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III - FUNCTIONAL DESCRIPTION (continued) III.5 - Memory Interface III.5.1 - Function Description The memory interface allows the connection of Static or Dynamic RAM. The memory space addressablein the two configurationsis not the same. In the case of dynamicmemory (DRAM), the memory interface will address up to 16 Megabytes. In case of static memory (SRAM) only 1 Megabytewill be addressed. The memory location is always organized in 16 bits. The memory is shared between the Multi-HDLC and the microprocessor. The access to thememory is arbitrated by an internal function of the circuit: the bus arbitration. III.5.2 - Choice of memory versus microprocessor and capacity required The memory interface depends on the memory chips which are connected. As the memory chips will be chosen versus the microprocessor and the wanted memory space, the following table presents the different configurations DRAM and SRAM selection versus P. Table 22 : DRAM and SDRAM Selection versus P
Microprocessor and shared memory 8 bits Processor 16/32 bits Processor Number of Megabytes Number of Megawords 0.5 0.25 Shared memory size required by the application 1 0.5 2 1 4 2 8 4 16 8
Example 1 : if the application requires 16 bit mProcessor and 1 Megaword Shared memory size, three capabilities are offered : - 4 DRAM Circuits (256Kx16) or - 4 DRAM Circuits (1Mx4) or - 1 DRAM Circuit (1Mx16). Example 2 : if the application requires 8 bit mProcessor and 1 Megabyte Shared memory size, three capabilities are offered: - 2 DRAM Circuits (256Kx16) or - 8 SRAM Circuits (128Kx8) or - 2 SRAM Circuits (512kx8). Example 3 : for small applications it is possible to connect 2 SRAM Circuits (128Kx8) to obtain 256 Kilobytes shared memory. III.5.3 - Memory Cycle For SRAM and DRAM, the different cycles are programmable. See Memory Interface Configuration Regist. MICR (32)H on Page 88. Each cycle is equal to : p x 1/f with f the frequency of signal applied to the Crystal 1 input and p selected by the user. See page 9.
DRAM Circuits proposed Capacity 4 Megabits 16 Megabits 64 Megabits Capacity 1 Megabits 4 Megabits Organization 256Kx16 1Mx4 1Mx16 4Mx4 4Mx16 Organization 128Kx8 512kx8 4(128Kx8) 8(128Kx8) 2(512kx8) SRAM Circuits proposed Not possible 1(256Kx16) 2(256Kx16) 4(256Kx16) 4(1Mx4) 1(1Mx16) 8(1Mx4) 2(1Mx16) 16(1Mx4) 4(1Mx16) 4(4Mx4) 1(4Mx16) 8(4Mx4) 2(4Mx16)
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III - FUNCTIONAL DESCRIPTION (continued) III.5.4 - SRAM interface The SRAM space achieves 1 Mbyte max. It is always organized in 16 bits. The structure of the memory plane is shown in the following figures. Because of the different chips usable, 19 address wires and 8 NCE (Chip Enable) are necessary to address the 1 Mbyte. The NCE selects the Most or Least Significant Byte versus the value of A0 delivered by the P and the location of chip in the memory space. III.5.4.1 - 128K x 16 (up to 512K x 16) SRAM This memory can be obtained with two 128K x 8 SRAM circuits (up to eight circuits)
Signals NCE7 NCE6 NCE5 NCE4 NCE3 NCE2 NCE1 NCE0 A19 1 1 1 1 0 0 0 0 A18 1 1 0 0 1 1 0 0 A0 or equiv. 1 0 1 0 1 0 1 0
The Address bits delivered by the Multi-HDLC for 512K x n SRAM circuits are : ADM0/14 and ADM15/18 (19 bits) corresponding with A1/19 delivered by the P. Figure 26 :512K x 8 SRAM Circuit Memory Organization
ADM0/18, NWE, NOE are con necte d to each circuit 512K x 16 512K x 8 circuit NCE1 1 NCE0 0
DM8/15
DM0/7
The Address bits delivered by the Multi-HDLC for 128K x 8 SRAM circuits are : ADM0/14 and ADM15/16 (17 bits) corresponding with A1/17 delivered by the P. Figure 25 :n x 128K x 16 SRAM Memory Organization
ADM0/16, NWE, NOE are con nected to each circu it 128K x 16 128K x 8 circu it NCE7 7 NCE6 6
III.5.5 - DRAM Interface In DRAM, the memory space can achieve up to 16 megabytes organized by 16 bits. Eleven address wires, four NRAS and two NCAS are needed to select any byte in the memory. One NRAS signal selects 1 bank of 4 and the NCAS signals select the bytes concerned by the transfer (1 or 2 selecting a byte or a word). The DRAM memory interface is then defined. The "RAS only" refresh cycles will refresh all memory locations. The refresh is programmable. The frequency of the refresh is fixed by the memory requirements. III.5.5.1 - 256K x n DRAM Signals
Signals NRAS3 NRAS2 NRAS1 NRAS0 NCAS1 NCAS0 A20 1 1 0 0 A19 1 0 1 0 A0 6800
1 0
UDS LDS
The Address bits delivered by the Multi-HDLC for 256K x n DRAM circuits are : ADM0/8 (2 x 9 = 18 bits) corresponding with A1/18 delivered by the P. Figure 27 : 256K x 16 DRAM Circuit Organization
NCE5
5
NCE4
4
CAS1
CAS0 256K x 16
NCE3
3
NCE2
2
RAS3 7 6
NCE1
1 DM8/15
NCE0
0 DM0/7
RAS2 5 4
RAS1
3
2
III.5.4.2 - 512K x n SRAM
DM8/15 DM0/7
5464-22.EPS
Signals NCE1 NCE0
A0 or equiv. 1 0
RAS0
1
0
ADM0/8, NWE , NO E are connected to ea ch circuit.
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III - FUNCTIONAL DESCRIPTION (continued) III.5.5.2 - 1M x n DRAM Signals
Signals NRAS3 NRAS2 NRAS1 NRAS0 NCAS1 NCAS0 A22 1 1 0 0 A20 1 0 1 0 1 0 UDS LDS
NRAS 0 1 DM8/15 0 DM0/7
5464-24.EPS 5464-25.EPS
Figure 29 : 4M x 16 DRAM Circuit Organization
A0 6800
NCAS1 NCAS 0 4M x 16 NRAS 1 3 2
ADM0/10, NWE , NOE a re conne cte d to e ach circuit
The Address bits delivered by the Multi-HDLC for 1M x n DRAM circuits are : ADM0/9 (2 x 10 = 18 bits) corresponding with A1/20 delivered by the P. Figure 28 : 1M x 16 DRAM Circuit Organization
NCAS1 NCAS0 1M x 16 NRAS3 7 6
NRAS2
5
4
NRAS1
3
2
NRAS0
1 DM8/15
0
5464-23.EPS
DM0/7
III.6 - Bus Arbitration The Bus arbitration function arbitrates the access to the bus between different entities of the circuit. Those entities which can call for the bus are the following : - The receive DMA controller, - The microprocessor, - The transmit DMA controller, - The Interrupt controller, - The memory interface for refreshing the DRAM. This list gives the memory access priorities per default. If the treatment of more than 32 HDLC channels is required by the application, it is possible to chain several Multi-HDLC components.That is done with two external pins (TRI, TRO) and a token ring system. The TRI, TRO signals are managed by the bus arbitration function too. When a chip has finished its tasks, it sends a pulse of 30 ns to the next chip. Figure 30 : Chain of n Multi-HDLC Components
ADM0/9, NWE, NOE are connected to ea ch circuit
III.5.5.3 - 4M x n DRAM Signals
Signals NRAS1 NRAS0 NCAS1 NCAS0 A23 1 0 1 0 A0 or equiv.
P
TRI MHDLC 0 RAM TRO
TRI MHDLC 1 TRO
The Address bits delivered by the Multi-HDLC for 4M x n DRAM circuits are : ADM0/10 (2 x 11 = 22 bits) corresponding with A1/22 delivered by the P.
TRI MHDLC n P Bus TRO RAM Bus
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III - FUNCTIONAL DESCRIPTION (continued) III.7- Clock Selection and Time Synchronization III.7.1 - Clock Distribution Selection and Supervision Two clock distributions are available: Clock at 4.096 MHz or 8.192 MHz and a synchronization signal at 8 KHz. The component has to select one of these two distributions and to check its integrity. See Fig. 31 MHDLC clock generation. Two other clock distributions are allowed: Clock at 3072 MHz or 6144 MHz and a synchronization signal at 8 KHz. See General ConfigurationRegister GCR (02)H on page 61 DCLK, FSC GCI and FSC V* are output on three external pins of the Multi-HDLC. DCLK is the clock selected between Clock A and Clock B. FSC, GCI and FSC V* are functions of the selected distribution and respect the GCI and V* frame synchronization specifications. The supervision of the clock distribution consists of verifying its availability. The detection of the clock absence is done in a less than 250 microseconds. In case the clock is absent, an interrupt is generated with a 4 kHz recurrence. Then the clock distribution is switched automatically up to detection of couple A or couple B. When a couple is detected the change of clock occurs on a falling edgeof the new selecteddistribution.Moreover the Figure 31 : MHDLC Clock Generation
REF. CLOCK RESET INT1
clock distribution can be controlled by the microprocessor thanks to SELB, bit of General Configuration Register. Depending on the applications, three different signals of synchronization (GCI, V* or Sy) can be provided to the component. The clock A/B frequency can be a 4096 or 8192kHz clock. The component is informed of the synchronization and clocks that are connected by software.The timings of the different synchronization are given page 45.
III.7.2 - VCXO Frequency Synchronization An external VCXO can be used to provide a clock to the transmission components. This clock is controlled by the main clock distribution (Clock A or Clock B at 4096kHz). As the clock of the transmission component is 15360 or 16384kHz,a configurable function is necessary. The VCXO frequency is divided by P (30 or 32) to provide a common sub-multiple (512kHz) of the referen ce frequency CLOCKA or CLOCKB (4096kHz). The comparison of these two signals gives an error signal which commands the VCXO. Two external pins are needed to perform this function : VCXO-INand VCXO-OUT (see Figure 32 on Page 42).
FRAME A CLOCK A
Clock Lack Detection from 2 50s CLOCK S ELECTION Fra me Clock CLOCK
FSCV* FSCGCI ADAPTATION DCLK
FRAME B CLOCK B
At RES ET FRAME A a n d CLOCK A are s e lecte d
Se lect A o r B (S ELB)
Clock S upe rvision Dea ctivation (CS D) A or B S elected (BSEL)
HCL
S YN1
SYN0
To th e inte rna l MHDLC
GENERAL CONFIGURATION REGISTER (GCR)
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III - FUNCTIONAL DESCRIPTION (continued) Figure 32 : VCXO Frequency Synchronization
VCXO f = 15360kHz or 1 6384kHz 7 VCXO IN /8 if f = 1536 0kHz, p = 30 if f = 1638 4kHz, p = 32 Ref = 4 096kHz MHDLC EVM /p
OUX
LOW P ASS FILTER
8 VCXO OUT
III.8 - Interrupt Controller III.8.1 - Description Three external pins are used to manage the interrupts generated by the Multi-HDLC. The interrupts have three main sources : - The operating interrupts generated by the HDLC receivers/transmitters, the CI receivers and the monitor transmitters/receivers. INT0 Pin is reserved for this use. - The interrupt generated by an abnormal working of theclockdistribution.INT1Pinisreservedforthisuse. - The non-activity of the microprocessor (Watchdog). WDO Pin is reserved for this use. III.8.2 - Operating Interrupts (INT0 Pin) There are five main sources of operating interrupts in the Multi-HDLC circuit : - The HDLC receiver, - The HDLC transmitter, - The CI receiver, - The Monitor receiver, - The Monitor transmitter. When an interrupt is generated by one of these functions, the interrupt controller : - Collects all the information about the reasons of this interrupt, - Stores them in external memory, - Informs the microprocessor by positioning the INT0 pin in the high level. Three interruptqueues are built in externalmemory to store the information about the interrupts : - A single queue for the HDLC receiversand transmitters, - One for the CI receivers, - One for the monitor receivers. The microprocessor takes the interrupts into account by reading the Interrupt Register (IR) of the interrupt controller.
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This register informs the microprocessor of the interrupt source. The microprocessor will have information about the interrupt source by readingthe corresponding interrupt queue (see Paragraph"Interrupt Register IR (38)H" on Page 91). On an overflow of the circular interrupt queues and an overrun or underrun of the different FIFO, the INT0 Pin is activated and the origin of the interrupt is stored in the Interrupt Register. A 16 bits register is associated with the Tx Monitor interrupt. It informs the microprocessor of which transmitter has generated the interrupt (see Paragraph "Transmit Monitor Interrupt Register TMIR (30)H" on Page 88). III.8.3 - Time Base Interrupts (INT1 Pin) The Time base interrupt is generated when an absence or an abnormal working of clock distribution is detected. The INT1 Pin is activated. III.8.4 - Emergency Interrupts (WDO Pin) The WDO signal is activated by an overflow of the watchdog register. III.8.5 - Interrupt Queues There are three different interrupt queues : - Tx and Rx HDLC interrupt queue, - Rx C/I interrupt queue, - Rx Monitor interrupt queue. Their length can be defined by software. For debugging function, each interrupt word of the CI interrupt queue and monitor interrupt queue can be followedby a time stamped word. It iscomposed of a counter which runs in the range of 250s. The counter is the same as the watchdog counter. Consequently,the watchdogfunction isn't available at the same time.
5464-27.EPS
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III - FUNCTIONAL DESCRIPTION (continued) Figure 33 : The Three Circular Interrupt Memories
IBA INITIALIZATION BLOC K IBA + 256 HDLC (Tx a nd Rx) INTERR UP T QUEUE IBA + 256 + HDLC Que ue S ize IBA + 256 + HDLC Que ue S ize + MON Que ue S ize
MON (Rx) INTER RUPT QUEUE
C/I (Rx) INTER RUP T QUEUE
IBA + 254
III.9 - Watchdog This function is used to control the activity of the application. It is composed of a counter which counts down from an initial value loaded in the Timer register by the microprocessor. If the microprocessor doesn't reset this counter before it is totally decremented, the external Pin WDO is activated ; this signal can be used to reset the microprocessor and all the application. The initial time value of the counter is programmable from 0 to 15s in increments of 0.25ms. At the reset of the component,the counter is automatically initialized by the value corresponding to 512ms which are indicated in the Timer register. The microprocessor must put WDR (IDCR Register) to"1" to reset this counter and to confirm that the application started correctly. In the reverse case, the WDO signal could be used to reset the board a second time. The FS signal (8kHz) divided by two or the XTAL1 signal (typically 32768kHz) divided by 8192 can be selected to increment the counter. At reset the watchdog is incremented by the XTAL1 signal.
III.10 - Reset There are two possibilities to reset the circuit : - by software, - by hardware. Each programmable register receives its default value. After that, the default value of each data register is stored in the associated memory except for Time slot Assigner memory.
III.11 - Boundary Scan The Multi-HDLC is equipped with an IEEE Standard Test Access Port (IEEEStd1149.1).The boundary scan technique involves the inclusion of a shift register stage adjacent to each component pin so that signals at component boundaries can be controlled and observed using scan testing principle. Its intention is to enable the test of on board interconnectionsand ASIC production tests. The external interface of the Boundary Scan is composed of the signals TDI, TDO, TCK, TMS and TRST as defined in the IEEE Standard.
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The values indicated in the tables from pag. 44 to pag. 67 are referred to VDD = 5V if not otherwise specificated. IV - DC SPECIFICATIONS IV.1 - Absolute Maximum Ratings
Symbol VDD T stg 5V Power Supply Voltage Input or Output Voltage Storage Temperature Parameter Value -0.5, 6.5 -0.5, VDD + 0.5 -55, +125 Unit V V C
IV.2 - Power Dissipation
Symbol P Parameter Power Dissipation Test Conditions VDD = 5V VDD = 3.3V Min. Typ. 300 100 Max. 400 130 Unit mW mW
IV.3 - Recommended DC Operating Conditions
Symbol VDD Toper Parameter 5V Power Supply Voltage 3.3V Power Supply Voltage Operating Temperature Test Conditions Min. 4.75 3 -40 Typ. Max. 5.25 3.6 +85 Unit V V C
Note 1 : All the following specifications are valid only within these recommended operating conditions.
IV.4 - TTL Input DC Electrical Characteristics
Symbol VIL VIH IIL IIH Vhyst VT+ VTC IN C OUT CI/O Parameter Low Level Input Voltage High Level Input Voltage Low Level Input Current High Level Input Schmitt Trigger hysteresis Positive Trigger Voltage Negative Trigger Voltage Input Capacitance (see Note 2) Output Capacitance Bidirextional I/O Capacitance 4 Test Conditions VDD = 5V; V DD = 3.3V VDD = 5V; V DD = 3.3V VI = 0V VI = VDD VDD = 5V VDD = 3.3V VDD = 5V VDD = 3.3V VDD = 5V VDD = 3.3V f = 1MHz @ 0V 0.6 0.6 0.4 0.3 0.7 0.5 2 1.4 0.8 0.9 2 4 8 4 2.0 1 -1 1 0.8 2.4 2 Min. Typ. Max. 0.8 Unit V V A A V V V V V V pF
Note 2 : Excluding package
IV.5 - CMOS Output DC Electrical Characteristics
Symbol VOL VOH
Note 3 :
Parameter Low Level Output Voltage High Level Output Voltage
Test Conditions IOL = X mA (see Note 3) IOH = -X mA (see Note 3)
Min. VDD5-0.4
Typ.
Max. 0.4
Unit V V
X is the source/sink current under worst case conditions and is reflected in the name of the I/O cell according to the drive capability. X = 4 or 8mA.
IV.6 - Protection
Symbol VESD Parameter Electrostatic Protection Test Conditions C = 100pF, R = 1.5k Min. 2000 Typ. Max. Unit V
44/101
STLC5465B
V - CLOCK TIMING V.1 - Synchronization Signals delivered by the system For one of three different input synchronizations which is programmed, FSCG and FSCV* signals delivered by the Multi-HDLC are in accordance with the figure hereafter. Figure 34 : Clocks received and delivered by the Multi-HDLC
CLOCK B t2 CLOCK A 3 4 5 6 7 0 1 t5h t5l t1
1) S y Mode Fra me A (or B) t3 t4 t3 t4 t3 2) G CI Mod e Fra me A (or B) t4 CGI
3) V*Mode Fra me A (or B) DIN 0/8, ECHO DOUT 0/7, CB if FS = FS CG TDM0/7 FS CG de livere d by the circuit FS CV* de livere d by the circuit Bit3 Bit4 Bit5 Time S lot 31 Bit6 Bit7 Bit0 Bit1
Time S lot 0
The four Multiplex Configura tion Re giste rs a re a t ze ro (no de lay).
Symbol t1 t2 t3 t4 t4GCI t5 t6
Parameter Clock Period if 4096kHz (3072) Clock Period if 8192kHz (6144) Delay between Clock A and Clock B Set up time Frame A (or B)/CLOCK A (or B) Hold time Frame A (or B)/CLOCK A (or B) Clock ratio t5h/t5l Duration of FSCG
Min. 239 (320) 120 (158) - 60 10 10 10 75
Typ. 244 (325) 122 (162) 0
Max. 249 (330) 125 (165) +60 t1-10 t1-10 125000 - (t1 - 10)
Unit ns ns ns ns ns % ns
100 488
125
45/101
5464-29.EPS
t6
STLC5465B
V - CLOCK TIMING (continued) V.2 - TDM Synchronization Figure 35 : Synchronization Signals received by the Multi-HDLC
CLOCK A (or B) t2 DCLK delivered by the Multi-HDLC t3 FS delivered by the Multi-HDLC t6 DOUT0/7, CB Bit 7, Time Slot 31 Bit 0, Time Slot 0 t7 DIN0/8 t9 t8 ECHO t7 t4 t1
t5
The four Multiplex Configuration Registers are at zero (no delay between FS and Multiplexes).
Symbol t1 t2
Parameter DCLK Clock Period if 4096kHz (3072) DCLK Clock Period if 2048kHz (1536) Delay between CLOCK A or B and DCLK (30pF) V DD = 5V V DD = 3.3V Set-up Time FS/DCLK Hold Time FS/DCLK Duration FS DCLK to Data 50pF DCLK to Data 100pF Set-up Time Data/DCLK Hold Time Data/DCLK Set-up Echo/DCLK (rising edge) Hold Time Echo/DCLK (rising edge)
Min. Id CLOCKA or B
Typ. 244 (325) 488 (651) 5 20
Max. Id CLOCKA or B 30 32 t1-20 125000-244 50 100
Unit ns ns ns ns ns ns ns ns ns ns
t3 t4 t5 t6 t7 t7 t8 t9
20 20 244 (325)
20 20 155 205
ns ns
46/101
STLC5465B
V - CLOCK TIMING (continued) V.3 - GCI Interface Figure 36 : GCI Synchro Signal delivered by the Multi-HDLC
125 s FS rece ived by the Multi-HDLC CH0 DIN4/5 DOUT4/5 CH1 CH7
GCI Cha nn e l B1 B2 MON D C/I AE
t1 DCLK de livere d by the Multi-HDLC t3 FS CG de livere d by the Multi-HDLC t6 DOUT0/7, CB if FS CG is conne cted to FS Bit 0, Time S lot 0 t7 DIN0/8
5464-31.EPS
t3
t7
The four Multiplex Configura tion Registers a re a t ze ro (no delay be twe en FS a nd Multiplexes ).
Symbol t1 t3 t5 t6 t7 t7
Parameter DCLK Clock Period if 4096kHz (3072) DCLK Clock Period if 2048kHz (1536) DCLK to FSCG Duration FS DCLK to Data 50pF DCLK to Data 100pF Set-up Time Data/DCLK Hold Time Data/DCLK
Min. Id CLOCK A or B
Typ. 244 (325) 488 (651) 244
Max. Id CLOCK A or B 20 125000-244 50 100
Unit ns ns ns ns ns ns ns ns
20 20
47/101
STLC5465B
V - CLOCK TIMING (continued) V.4 - V* Interface Figure 37 : V* Synchronization Signal delivered by the Multi-HDLC
125 s FS re ce ive d by the Multi-HDLC CH0 DIN4/5 DOUT4/5 CH1 CH7
GCI Ch a nn e l B1 B2 MON D C/I AT
t1 DCLK de livere d by the Multi-HDLC t3 FSCV* de live re d by the Multi-HDLC DOUT0/7, CB if FSCG is conne cte d to FS Bit 3, Time S lot 31 t7 DIN0/8
5464-32.EPS
t3
t7
The four Multiple x Configura tion Re giste rs a re a t z e ro (no de la y be twe e n FS a nd Multiple xe s). Symbol t1 t3 t5 t6 t7 t7 Clock Period 4096kHz DCLK to FSCV* Duration FSCV* Clock to Data 50pF Clock to Data 100pF Set-up Time Data/DCLK Hold Time Data/DCLK 20 20 244 50 100 Parameter Min. Typ. 244 20 Max. Unit ns ns ns ns nS ns ns
48/101
STLC5465B
V1 - MEMORY TIMING VI.1 - Dynamic Memories Figure 38 : Dynamic Memory Read Signals from the Multi-HDLC
NDS fro m P (or equivalent) MASTE RCLOCK a pplied to XTAL1 P in T a a Tota l Rea d Cycle 1/f a a a HZ Tu HZ a
NRAS 0/3
NCAS 0/1 NWE
Tv
Tw
Tz
Tv/2 ADM0/10
NOE
Tw + Tz/2 Ts Th
DM0/15 from DRAM Circuit No te : S e e MBL De finition Ea ch s ignal from the MHDLC is high impeda nce outside this time if MBL = 0
5464-33.EPS
HZ
HZ
Symbol T a
Parameter Delay between Data Strobe from the mP and beginning of cycle Delay between Masterclock and Edge of each signal delivered by the MHDLC (30pF) V DD = 5V V DD = 3.3V Delay between NCAS Falling Edge and NCAS rising Edge Delay between NCAS Rising Edge and end of cycle Set-up Time Data /NCAS Rising Edge Hold Time Data/NCAS Rising Edge
Min. 2/f
Typ.
Max.
Unit
20 30 1/f 1/f 20 0
40 2/f 2/f
ns ns ns ns ns ns
Tw Tz Ts Th
49/101
STLC5465B
VI - MEMORY TIMING (continued) Figure 39 : Dynamic Memory Write Signals from the Multi-HDLC
NDS fro m P (or equivalent) MASTE RCLOCK a pplied to XTAL1 P in T a a Total Write Cycle 1/f a a a HZ Tu HZ a
NRAS 0/3
NCAS 0/1
Tv
Tw
Tz
NWE Tv/2 ADM0/10 Td DM0/15 NOE No te : S e e MBL De finition Ea ch s ignal from the MHDLC is high impeda nce outside this time if MBL = 0
5464-34.EPS
HZ
HZ
Symbol f Tu Tv Tw Tz Tv/2 Td f : Masterclock Frequency
Parameter Delay between beginning of cycle and NRAS Falling Edge Delay between NRAS Falling Edge and NCAS Falling Edge Delay between NCAS Falling Edge and NWE Rising Edge Delay between NWE Rising Edge and end of cycle Delay between NRAS Falling Edge and address change Data Valid after beginning of cycle (30 pF)
Min. 32 1/f 1/f 1/f 1/f 1/2f 1/f
Typ.
Max. 33 2/f 2/f 2/f 2/f 1/f 1/f
Unit MHz ns ns ns ns ns ns
Note : Total Cycle : Tu + Tv + Tw + Tz
50/101
STLC5465B
VI - MEMORY TIMING (continued) VI.2 - Static Memories Figure 40 : Static Memory Read Signals from the Multi-HDLC
NDS fr om P (or e quivalent) MASTERCLOCK applied to XTAL1 P in T a a HZ a HZ Tota l Re ad Cycle 1/f a
ADM0/18
NCE 0/7 NWE NOE HZ Twz Ts DM0/15 from S RAM Circuit Note : S e e MBL De finition E ach s ignal delivere d by the MHDLC is high impe dance outs ide this time
5464-35.EPS
HZ Th
Symbol T 1/f a
Parameter Delay between Data Strobe delivered by the mP and beginning of cycle f: Masterclock frequency Total read cycle: Twz + 1/f Delay between Masterclock and Edge of each signal delivered by the MHDLC (30pF) V DD = 5V V DD = 3.3V NOE width Set-up Time Data /NOE Rising Edge Hold Time Data /NOE Rising Edge
Min. 2/f
Typ.
Max.
Unit
20 30 1/f 20 0
40 4/f
ns ns ns ns ns
Twz Ts Th
51/101
STLC5465B
VI - MEMORY TIMING (continued) Figure 41 : Static Memory Write Signals from the Multi-HDLC
NDS from P (or equivalent) MASTERCLOCK applied to XTAL1 Pin
T a a HZ
Total Write Cycle 1/f a a HZ a
ADM0/18
NCE0/7
Tuv
NWE NOE DM0/15
5464-36.EPS
Note : See MBL Definition
HZ
Each signal delivered by the MHDLC is high impedance outside this time
HZ
Symbol T 1/f a
Parameter Delay between Data Strobe delivered by the P and beginning of cycle f : Masterclock frequency Delay between Masterclock and Edge of each signal delivered by the MHDLC (30pF) V DD = 5V V DD = 3.3V NCE width
Min. 2/f
Typ.
Max.
Unit
30 1/f
20 40 4/f
ns ns ns
Tuv
Note : Total Write Cycle : Tuv + 1/f
52/101
STLC5465B
VII - MICROPROCESSOR TIMING VII.1 - ST9 Family MOD0=1, MOD1=0, MOD2=0 Figure 42 : ST9 Read Cycle
NCS0/1
t1
READY
t2
t3
NAS/ALE
t4
t12 t11
NDS/NRD
t5
AD0/7
A0/7
t6
t7
t8 D0/7
t10
R/W / NWR
Symbol t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12
t9
Parameter Delay Ready / Chip Select (if t3 > t1), (30pF) Delay when immediate access Hold Time Chip Select /Data Strobe Delay Ready / NAS (if t1 > t3), (30pF) Delay when immediate access Width NAS Set-up Time Address / NAS Hold Time Address / NAS Data Valid after Ready Data Valid after Data Strobe (30pF) Set-up Time R/W /NAS Hold Time R/W / Data Strobe Width NDS when immediate access Delay NDS / NCS
Min. 0
Typ.
Max. 98
Unit ns ns ns ns ns ns ns ns
14 0 98 20 9 9 0 0 15 15 50 5 15 15
ns ns ns ns ns ns
53/101
5464-37.EPS
STLC5465B
VII - MICROPROCESSOR TIMING (continued) Figure 43 : ST9 Write Cycle
NCS0/1
t1
READY
t2
t3
NAS/ALE
t4
t12 t11
NDS/NRD
t7 t5
AD0/7
A0/7
t6 D0/7
t8
t9
R/W / NWR
t10
5464-38.EPS
Symbol t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12
Parameter Delay Ready / Chip Select (if t3 > t1), (30pF) Delay when immediate access Hold Time Chip Select / Data Strobe Delay Ready / NAS (if t1 > t3), (30pF) Delay when immediate access Width NAS Set-up Time Address / NAS Hold Time Address / NAS Set-up Time Data / Data Strobe Hold Time Data / Data Strobe Set-up Time R/W / NAS Hold Time R/W / Data Strobe Width NDS when immediate access Delay NDS / NCS
Min. 0
Typ.
Max. 98
Unit ns NS ns ns NS ns ns ns ns ns ns ns ns ns
14 0 98 20 9 9 -15 15 15 15 50 5
54/101
STLC5465B
VII - MICROPROCESSOR TIMING (continued) VII.2 - ST10/C16x mult. A/D, MOD0 = 1, MOD1 = 0, MOD2 = 1 Figure 44 : ST10 (C16x) Read Cycle; Multiplexed A/D
NCS0/1 t2 NDSACK 0/ DTAC K / NREADY NAS/ ALE ND S/ NRD t4 t12 t7 t1 t3
t8
D0/15 R/W / NWR A0/15 / AD0/15 A16/23 NBHE
Symbol t1 Parameter Delay Not Ready/NRD (if NCS0/1 = 0), (30pF) Delay when immediate access Hold Time Chip Select / NRD Delay Not Ready / NRD rising edge Delay when immediate access Width ALE Set-up Time Address / ALE Hold Time Address /ALE V DD = 5V V DD = 3.3V t7 t8 t9 t10 t12 Data valid after ready Data bus at high impedance after NRD (30pF) Set-up Time NBHE, Address A 16/23/ALE Hold Time NBHE / NRD Delay NRD / NCS 5 10 0 0 5 10 0 15 15 ns ns ns ns ns ns ns V DD = 5V V DD = 3.3V 20 5 V DD = 5V V DD = 3.3V 10 0 98 108 Min. 0 98 108 Typ. Max. Unit ns ns ns ns ns ns ns ns ns
t9
t10
t2 t3
t4 t5 t6
55/101
STLC5465B
VII - MICROPROCESSOR TIMING (continued) Figure 45 : ST10 (C16x) Write Cycle; Multiplexed A/D
NCS0/1 t2 NDSACK0/ NDTAC K / NREADY t4 NA S / ALE ND S/ NRD t12 t5
A0/15
t1 t3
t6
D0/15
t8
AD0/15 R/W / NWR t9 NBHE A16/23
t7 t10
Symbol t1
Parameter Delay Not Ready/ALE (if NCS0/1 = 0), (30pF) Delay when immediate access Hold Time Chip Select / NWR Delay Not Ready / NRD rising edge Delay when immediate access Width ALE Set-up Time Address / ALE Hold Time Address /ALE V DD = 5V V DD = 3.3V V DD = 5V V DD = 3.3V V DD = 5V V DD = 3.3V
Min. 0
Typ.
Max. 98 108
Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
t2 t3
10 0 98 108 20 5 5 10 -15 0 5 10 0
t4 t5 t6
t7 t8 t9 t10 t12
Set up time Data/NWR Set up time NBHE-Address A 16/23/ALE Set-up Time NBHE, Address A 16/23/ALE Hold Time NBHE / NWR Delay NWR / NCS
56/101
STLC5465B
VII - MICROPROCESSOR TIMING (continued) VII.3 - ST10/C16x demult. A/D, MOD0 = 0, MOD1 = 1, MOD0 = 1 Figure 46 : ST10 (C16x) Read Cycle; Demultiplexed A/D
NCS0/1 t2 NDSACK 0/ DTAC K / NREADY NAS/ ALE ND S/ NRD t4 t12 t7 t8 t1 t3
D0/15 R/W / NWR A0/15 / AD0/15 A16/23 NBHE
t9
t10
Symbol t1
Parameter Delay Not Ready/NRD (if NCS0/1 = 0), (30pF) Delay when immediate access Hold Time Chip Select / NRD Delay Not Ready / NRD rising edge Delay when immediate access Width ALE Data valid after NOTREADY falling efge (30pF) Data bus at high impedance after NRD (30pF) Set-up Time NBHE, Address AD0/15, A16/ALE Hold Time NBHE / Address ADO/15, A16/23/NRD Delay NRD / NCS V DD = 5V V DD = 3.3V V DD = 5V V DD = 3.3V
Min. 0
Typ.
Max. 98 108
Unit ns ns ns ns ns ns ns ns ns ns ns ns ns
t2 t3
10 0 98 108 20 0 0 5 10 0 15 15
t4 t7 t8 t9 t10 t12
57/101
STLC5465B
VII - MICROPROCESSOR TIMING (continued) Figure 47 : ST10 (C16x) Write Cycle; Demultiplexed A/D
NCS0/1 t2 NDSACK0/ DTACK / NREADY t4 NA S/ ALE ND S/ NRD t12 t8 t1 t3
D0/15 R/W / NWR AD0/15
t7 t9 t10
Symbol t1
Parameter Delay Not Ready/NWR (if NCS0/1 = 0), (30pF) Delay when immediate access Hold Time Chip Select / NRD Delay Not Ready / NWR rising edge Delay when immediate access Width ALE Set up time Data/NWR Hold time Data/NWR Set-up Time NBHE, Address AD0/15, A16/23/ALE Hold Time NBHE, Address AD0/15, A16/23 NWR Delay NWR / NCS V DD = 5V V DD = 3.3V V DD = 5V V DD = 3.3V
Min. 0
Typ.
Max. 98 108
Unit ns ns ns ns ns ns ns ns ns ns ns ns ns
t2 t3
10 0 98 108 20 -15 15 5 10 0
t4 t7 t8 t9 t10 t12
58/101
STLC5465B
VII - MICROPROCESSOR TIMING (continued) VII.4 - 80C188 MOD0=1, MOD1=1, MOD2=0 Figure 48 : 80C188 Read Cycle
NCS0/1
t1
READY
t2
t3 NAS/ALE t4
NDS/NRD t5
AD0/7
A0/7
t12 t7 t6 t8 D0/7
5464-39.EPS
R/W / NWR Symbol t1 Parameter Delay Ready / Chip Select (if t3 > t1), (30pF) Delay when immediate access Hold Time Chip Select / NRD Delay Ready / ALE (if t1 > t3), (30pF) Delay when immediate access Width ALE Set-up Time Address / ALE Hold Time Address / ALE V DD = 5V V DD = 3.3V t7 t8 t12 Data Valid after Ready Data Valid after NRD (30pF) Delay NDS / NCS 5 10 0 0 0 15 ns ns ns ns ns V DD = 5V V DD = 3.3V 20 5 V DD = 5V V DD = 3.3V 10 0 98 108 Min. 0 98 108 Typ. Max. Unit ns ns ns ns ns ns ns ns ns
t2 t3
t4 t5 t6
59/101
STLC5465B
VII - MICROPROCESSOR TIMING (continued) Figure 49 : 80C188 Write Cycle
NCS0/1 t1 READY t3 NAS/ALE NDS/NRD t5 AD0/7
A0/7
t2
t4
t12 t6 D0/7
t8
R/W / NWR
t7
Symbol t1
Parameter Delay Ready / Chip Select (if t3 > t1), (30pF) Delay when immediate access Hold Time Chip Select / NWR Delay Ready / ALE (if t1 > t3), (30pF) Delay when immediate access Width ALE Set-up Time Address / ALE Hold Time Address / ALE V DD = 5V V DD = 3.3V V DD = 5V V DD = 3.3V V DD = 5V V DD = 3.3V
Min. 0
Typ.
Max. 98 108
Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns
t2 t3
10 0 98 108 20 5 5 10 -15 15 0
t4 t5 t6
t7 t8 t12
Set-up Time Data / NWR Hold Time Data / NWR Delay NWR / NCS
60/101
5464-40.EPS
STLC5465B
VII - MICROPROCESSOR TIMING (continued) VII.5 - 80C186 MOD0=1, MOD1=1, MOD2=1 Figure 50 : 80C186 Read Cycle
NCS0/1 t1 READY t3 NAS/ALE t4 t2
NDS/NRD t5 AD0/15 R/W / NWR t9 NBHE A16/19
A0/15
t12 t7 t6 t8 D0/15
t10
NBHE A16/19
t11 NBHE
5464-41.EPS
Symbol t1
Parameter Delay Ready / Chip Select (if t3 > t1), (30pF) Delay when immediate access Hold Time Chip Select / NRD Delay Ready / ALE (if t1 > t3), (30pF) Delay when immediate access Width ALE Set-up Time Address / ALE Hold Time Address / ALE VDD = 5V VDD = 3.3V Data Valid after Ready Data Valid after NRD (30pF) Set-up Time NBHE-Address A16/19 / ALE Hold Time Address A1619 / NRD Hold Time NBHE- / NRD Delay NRD / NCS V DD = 5V V DD = 3.3V V DD = 5V V DD = 3.3V
Min. 0
Typ.
Max. 98 108
Unit ns ns ns ns
t2 t3
10 0 98 108 20 5 5 10 0 0 5 10 10 0 15 15
ns ns ns ns ns ns ns ns ns ns ns ns
t4 t5 t6
t7 t8 t9 t10 t11 t12
61/101
STLC5465B
VII - MICROPROCESSOR TIMING (continued) Figure 51 : 80C186 Write Cycle
NCS0/1
t1
READY
t2
t3 NAS/ALE NDS/NRD t5
AD0/15
A0/15
t4
t12 t6 D0/15
t8
R/W / NWR t9
NBHE A16/19
NBHE A16/19
t7 t10 NBHE t11
5464-42.EPS
Symbol t1
Parameter Delay Ready / Chip Select (if t3 > t1), (30pF) Delay when immediate access Hold Time Chip Select / NWR Delay Ready / ALE (if t1 > t3), (30pF) Delay when immediate access Width ALE Set-up Time Address / ALE Hold Time Address / ALE V DD = 5V V DD = 3.3V V DD = 5V V DD = 3.3V V DD = 5V V DD = 3.3V
Min. 0
Typ.
Max. 98 108
Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
t2 t3
10 0 98 108 20 5 5 10 -15 15 5 10 10 0
t4 t5 t6
t7 t8 t9 t10 t11 t12
Set-up Time Data / NWR Hold Time Data / NWR Set-up Time NBHE-Address A16/19 / ALE Hold Time Address 16/19 / ALE Hold Time NBHE- / NWR Delay NWR / NCS
62/101
STLC5465B
VII - MICROPROCESSOR TIMING (continued) VII.6 - 68000 MOD0=0, MOD1=0, MOD2=1 Figure 52 : 68000 Read Cycle
NCS0/1
t1
NDTACK
t2 t4
t3
NAS/ALE
SIZE0/NLDS SIZE1/NUDS
A1/23 R/W / NWR
t6 t5
A1/23 t7 t8
5464-43.EPS
D0/15
Symbol t1 t2 t3 t4 t5 t6 t7 t8
Parameter Delay NDTACK / NCS0/1 (if t3 > t1), (30pF) Delay when immediate access Hold Time Chip Select / NLDS-NUDS Delay NDTACK / NLDS-NUDS Falling Edge (if t1> t3), (30pF) Delay when immediate access Delay NDTACK / NLDS-NUDS Rising Edge Set-up Time Address and R/W / last NLDS-NUDS or NCS Hold Time Address and R/W / NLDS-NUDS Data Valid after NDTACK Falling Edge (30pF) Data High Impedance after NLDS-NUDS Rising Edge (30pF)
Min. 0
Typ.
Max. 98
Unit ns ns ns ns ns ns ns ns
0 0 98 0 0 0 0 0 15 15 20
ns ns
63/101
STLC5465B
VII - MICROPROCESSOR TIMING (continued) Figure 53 : 68000 Write Cycle
NCS0/1
t1
NDTACK
t2 t4
t3
NAS/ALE
SIZE0/NLDS SIZE1/NUDS
A1/23 R/W / NWR
t6 t5
A1/23 t9 t10
5464-44.EPS
D0/15
Symbol t1 t2 t3 t4 t5 t6 t9 t10
Parameter Delay NDTACK / NCS0/1 (if t3 > t1), (30pF) Delay when immediate access Hold Time Chip Select / NLDS-NUDS Delay NDTACK / NLDS-NUDS Falling Edge (if t1> t3), (30pF) Delay when immediate access Delay NDTACK / NLDS-NUDS Rising Edge Set-up Time Address and R/W / last NLDS-NUDS or NCS Hold Time Address / NLDS-NUDS Set-up Time Data / NLDS-NUDS Hold Time Data / NLDS-NUDS
Min. 0
Typ.
Max. 98
Unit ns ns ns ns ns ns ns ns ns ns
0 0 98 20 0 0 15 10
64/101
STLC5465B
VII - MICROPROCESSOR TIMING (continued) VII.7 - 68020 MOD0=0, MOD1=0, MOD2=0 Figure 54 : 68020 Read Cycle
NCS0/1 t1 NDSACK0/ NDTACK NDSACK1/ READY NA S/ ALE t3 t4 t2
ND S/NRD SIZE0 /NLDS SIZE1 /NUDS t5 A 0/23 R/W /NWR t7 D0/15 t8 t6
Symbol t1 t2 t3 t4 t5 t6 t7 t8
Parameter Delay NDTACK / NCS0/1 (if t3 > t1), (30pF) Delay when immediate access Hold Time Chip Select / NDS rising edge Delay NDSACK1 / NDS Falling Edge (if t1> t3), (30pF) Delay when immediate access Delay NDSACK1 / NDS Rising Edge Set-up Time Address / NAS Hold Time Address / NDS Data valid before NDSACK1 falling edge (30pF) Data High Impedance after NDS (30pF)
Min. 0
Typ.
Max. 98
Unit ns ns ns ns ns ns ns ns
0 0 98 20 0 0 0 0 15 15
ns ns
65/101
STLC5465B
VII - MICROPROCESSOR TIMING (continued) Figure 55 : 68020 Write Cycle
NCS0/1 t1 NDSACK0/ NDTACK NDSACK1/ READY NA S / ALE t3 t4 t2
ND S/NRD SIZE0 /NLDS SIZE1 /NUDS t5 A 0/23 R/W /NWR t9 D0/15 t10 t6
Symbol t1 t2 t3 t4 t5 t6 t9 t10
Parameter Delay NDTACK / NCS0/1 (if t3 > t1), (30pF) Delay when immediate access Hold Time Chip Select / NDS rising edge Delay NDSACK1 / NDS Falling Edge (if t1> t3), (30pF) Delay when immediate access Delay NDSACK 1/ NDS Rising Edge Set-up Time Address / NAS Hold Time Address / NDS Set-up Time Data / NDS Hold Time Data / NDS
Min. 0
Typ.
Max. 98
Unit ns ns ns ns ns ns ns ns ns ns
0 0 98 20 0 0 0 10
66/101
STLC5465B
VII - MICROPROCESSOR TIMING (continued) VII.8 - Token Ring Timing Figure 56 : Token Ring
1/f MASTER CLOCK (applied to XTAL1 P in) a TRO tS TRI tH
5464-47.EPS
a
Symbol f a f : Masterclock frequency
Parameter Delay between Masterclock Rising Edge and Edges of TRO Pulse delivered by the MHDLC (10pF) V DD = 5V V DD = 3.3V Set-up Time TRI/Masterclock Masterclock Falling Edge Hold Time TRI/Masterclock Falling Edge
Min.
Typ. 32.768
Max.
Unit MHz
25 30 5 5 0
ns ns ns ns
tS tH
VII.9 - Master Clock Timing Figure 57 : Master Clock
1/f tH MASTER CLOCK (applied to XTAL1 Pin)
5464-48.EPS
tL
Symbol f 1/f tH tL Masterclock Frequency Masterclock Period Masterclock High Masterclock Low
Parameter
Min. 30 30.3 12 12
Typ. 32.768 30.5
Max. 33 33.3
Unit MHz ns ns ns
Crystal parameters: a) frequency b) Mode c) Resonance f (typically 32768.00 kHz) fundamental parallel
To reduce the drive level, the Crystal parameters can be: a) frequency f (typically 32768.00 kHz) b) Mode c) Resonance d) Load Capacity fundamental parallel Cl = 20pF
d) Load Capacity Cl= 30pF in accordance with 2 capacitors (47 pF each of them) the first capacitor is soldered nearest pin 2 (XTAL1) and nearest the ground, the second capacitor is soldered nearest pin 3 (XTAL2) and nearest the ground. e) Serial resistor 40 Ohms max
in accordance with 2 capacitors (33 pF each of them) e) Serial resistor 40 Ohms max N.B It is not necessary to add an external bias resistor between XTAL1 pin and XTAL2 pin. This resistor is inside the circuit.
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VIII - INTERNAL REGISTERS `Not used' bits (Nu) are accessible by the microprocessor but the use of these bits by software is not recommended. `Reserved' bits are not implemented in the circuit. However, it is not recommended to use this address. VIII.1 - Identification and Dynamic Command Register - IDCR (00)H
bit15 C15 C14 C13 C12 C11 C10 C9 bit8 C8 bit7 C7 C6 C5 C4 C3 C2 C1 bit 0 C0
When this register is read by the microprocessor, the circuit code C0/15 is returned. Reset has no effect on this register. C0/3 indicates the version. C4/7 indicates the revision. C8/11 indicates the foundry. C12/15 indicates the type. Example : this code is (0010)H for the first sample. When this register is written by the microprocessor then :
bit15 Nu Nu Nu Nu Nu Nu Nu bit8 Nu bit7 Nu Nu Nu Nu Nu RSS WDR bit 0 TL
: TOKEN LAUNCH When TL is set to 1 by the microprocessor, the token pulse is launched from the TRO pin (Token Ring Output pin). This pulse is provided to the TRI pin (Token Ring Input pin) of the next circuit in the applications where several Multi-HDLCs are connected to the same shared memory. WDR : WATCHDOG RESET. When the bit 1 (WDR) of this register is set to 1 by the microprocessor, the watchdog counter is reset. RSS : RESET SOFTWARE When the bit 2 (RSS) of this register is set to 1 by the microprocessor, the circuit is reset (Same action as reset pin). After writing this register, the values of these three bits return to the default value. VIII.2 - General Configuration - GCR (02)H
bit15 SBV MBL AFAB SCL BSEL SELB CSD bit8 HCL bit7 SYN1 SYN0 D7 EVM TSV TRD PMA bit 0 WDD
TL
After reset (0000)H
WDD
PMA
TRD
: Watch Dog Disable WDD = 1, the Watch Dog is masked : WDO pin stays at "0". WDD = 0, the Watch Dog generates an "1" on WDO pin if the microprocessor has not reset the Watch Dog during the duration programmed in Timer Register. : Priority Memory Access PMA = 1, if the token ring has been launched it is captured and kept in order to authorize memory accesses. PMA = 0, memory is accessible only if the token is present; after one memory access the token is re-launched from TRO pin of the current circuit to TRI pin of the next circuit. : Token Ring Disable TRD = 1, if the token has been launched, the token ring is stopped and destroyed ; memory accesses are not possible. The token will not appear on TRO pin. TRD = 0, the token ring is authorized; when the token will be launched,it will appear on TROpin.
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VIII - INTERNAL REGISTERS (continued) TSV : Time Stamping Validated TSV = 1, the time stamping counter becomes a free binary counter and counts down from 65535 to 0 in step of 250ms (Total = 16384ms). So if an event occurs when the counter indicates A and if the next event occurs when the counter indicates B then : t = (A-B) x 250ms is the time which has passedbetween the two events which have been stored in memoryby the InterruptController (for Rx C/I and Rx MON CHANNEL only). TSV = 0, the counter becomes a decimal counter.The Timer Register and this decimal counter constitute a Watch Dog or a Timer. : EXTERNAL VCXO MODE EVM=1,VCXO Synchronization Counter is divided by 32. EVM=0,VCXO Synchronization Counter is divided by 30. : HDLC connected to MATRIX D7 = 1, the transmit HDLC is connected to matrix input 7, the DIN7 signal is ignored. D7 = 0, the DIN7 signal is taken into account by the matrix, the transmit HDLC is ignored by the matrix.
EVM
D7
SYN0/1: SYNCHRONIZATION SYN0/1 : these two bits define the signal applied on FRAMEA/B inputs. For more details, see "Synchronization signals delivered by the system. V.1.
SYN1 0 0 1 1 SYN0 0 1 0 1 SYIinterface GCI Interface (the signal defines the first bit of the frame) Vstar Interface (the signal defines thrid bit of the frame) Not used Signal applied on FRAMEA/B inputs
HCL
: HIGH BIT CLOCK This bit defines the signal applied on CLOCKA/B inputs. HCL = 1, bit clock signal is at 8192kHz HCL= 0, bit clock signal is at 4096kHz CSD : Clock Supervision Deactivation CSD = 1, the lack of selected clock is not seen by the microprocessor; INT1 is masked. CSD = 0, when the selected clock disappears the INT1 pin goes to 5V, 250ms after this disappearance. SELB : SELECT B SELB = 1, FRAME B and CLOCK B must be selected. SELB = 0, FRAME A and CLOCK A must be selected. BSEL : B SELECTED (this bit is read only) BSEL = 1, FRAME B and CLOCK B are selected. BSEL = 0, FRAME A and CLOCK A are selected. SCL : Single Clock This bit defines the signal delivered by DCLK output pin. SCL = 1, Data Clock is at 2048kHz. SCL = 0, Data Clock is at 4096kHz. AFAB : Advanced Frame A/B Signal AFAB = 1, the advance of Frame A Signal and Frame B Signal is 0.5 bit time versus the signal frame A (or B) drawn in Figure 34. AFAB = 0, Frame A Signal and Frame B Signal are in accordance with the clock timing (see : Synchronization signals delivered by the Figure 45).
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VIII - INTERNAL REGISTERS (continued) MBL : Memory Bus Low impedance MBL = 1, the shared memory bus is at low impedance between two memory cycles. The memory bus includes Control bits, Data bits, Address bits. One Multi-HDLC is connected to the shared memory. MBL = 0, the shared memory bus is at high impedance between two memory cycles. Several Muti-HDLCs can be connected to the shared memory. One pull up resistor is recommended on each wire. : Six Bit Validation (A, E, S1/S4 bits). Global validation for 16 channels (Upstream and downstream). SBV = 1, in reception, the six bit word (A, E, S1/S4) located in the same timeslot as D channel can be received from any input timeslot; when this word is received identicaltwice consecutively, it is stored in the external shared memory and an interrupt is generated if not masked (like the reception of primitive from C/I channel). See "RECEIVE Command/Indicate INTERRUPT" on page 97. Sixteen independent detections are performed if the contents of any input timeslot is switched in the timeslot 4n+3 of two GCI multiplexes (corresponding to DOUT4 and DOUT5) with (0 n 7). Only the contents of D channel will be transmitted from input timeslot to GCI multiplexes. From ISDN channels to GCI channels on page 34. In transmission a six bit word (A, E, S1/S4) can be transmittedcontinuouslyto any output timeslot via the TCIR. See "Transmit Command/Indicate Register TCIR (2A)H" on page 76. This word (A, E, S1/S4) is set instead of primitive (C1, C2, C3, C4) and A, E bits received from the timeslot 4n+3 of two GCI multiplexes and the new contents of this timeslot 4n+3 must be switched on the selected output timeslot. SBV=0, the 16 six bit detections are not validated.
SBV
VIII.3 - Input Multiplex Configuration Register 0 - IMCR0 (04)H
bit15 bit8 bit7 bit 0 LP3 DEL3 ST(3)1 ST(3)0 LP2 DEL2 ST(2)1 ST(2)0 LP1 DEL1 ST(1)1 ST(1)0 LP0 DEL0 ST(0)1 ST(0)0 After reset (0000)H
See definition in next Paragraph. VIII.4 - Input Multiplex Configuration Register 1 - IMCR1 (06)H
bit15 bit8 bit7 bit 0 LP7 DEL7 ST(7)1 ST(7)0 LP6 DEL6 ST(6)1 ST(6)0 LP5 DEL5 ST(5)1 ST(5)0 LP4 DEL4 ST(4)1 ST(4)0 After reset (0000)H
ST(i)0 : STEP0 for each Input Multiplex i(0 i 7), delayed or not. ST(i)1 : STEP1 for each Input Multiplex i(0 i 7), delayed or not. DEL(i); : DELAYED Multiplex i(0 i 7).
DEL (i) ST (i) 1 ST (i) 0 X 1 1 1 0 0 0 0 0 1 1 0 1 1 0 1 0 1 1 0 1 STEP for each Input Multiplex 0/7 delayed or not Each received bit is sampled at 3/4 bit-time without delay. First bit of the frame is defined by Frame synchronization Signal. Each received bit is sampled with 1/2 bit-time delay. Each received bit is sampled with 1 bit-time delay. Each received bit is sampled with 2 bit-time delay. Each received bit is sampled with 1/2 bit-time advance. Each received bit is sampled with 1 bit-time advance Each received bit is sampled with 2 bit-time advance.
When IMTD = 0 (bit of SMCR), DEL = 1 is not taken into account by the circuit. 1/2 bit time 244ns if TDM at 2048 kHz, 1/2 bit time 122ns if TDM at 4096 kHz.
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VIII - INTERNAL REGISTERS (continued) LP (i) : LOOPBACK 0/7 LPi = 1, OutputMultiplex i is put instead of Input Multiplex i (0 i 7). LOOPBACK is transparent or not in accordance with OMVi (bit of Output Multiplex Configuration Register). LPi = 0, Normal case, Input Multiplex i(0 i 7) is taken into account.
N.B. If DIN4 and DIN5 are GCI Multiplexes : then ST(4)1 = ST(4)0 = 0 and ST(5)1 = ST(5)0 = 0 normally.
VIII.5 - Output Multiplex Configuration Register 0 - OMCR0 (08)H
bit15 bit8 bit7 bit 0 OMV3 DEL3 ST(3)1 ST(3)0 OMV2 DEL2 ST(2)1 ST(2)0 OMV1 DEL1 ST(1)1 ST(1)0 OMV0 DEL0 ST(0)1 ST(0)0 After reset (0000)H
See definition in next Paragraph. VIII.6 - Output Multiplex Configuration Register 1 - OMCR1 (0A)H
bit15 bit8 bit7 bit 0 OMV7 DEL7 ST(7)1 ST(7)0 OMV6 DEL6 ST(6)1 ST(6)0 OMV5 DEL5 ST(5)1 ST(5)0 OMV4 DEL4 ST(4)1 ST(4)0 After reset (0000)H
ST(i)0 : STEP0 for each Output Multiplex i(0 i 7), delayed or not. ST(i)1 : STEP1 for each Output Multiplex i(0 i 7), delayed or not. DEL(i); : DELAYED Multiplex i(0 i 7).
DEL (i) ST (i) 1 ST (i) 0 STEP for each Output Multiplex 0/7 delayed or not X 0 0 Each bit is transmitted on the rising edge of the double clock without delay. Bit 0 is defined by Frame synchronization Signal. 1 0 1 Each bit is transmitted with 1/2 bit-time delay. 1 1 0 Each bit is transmitted with 1 bit-time delay. 1 1 1 Each bit is transmitted with 2 bit-time delay. 0 0 1 Each bit is transmitted with 1/2 bit-time advance. 0 1 0 Each bit is transmitted with 1 bit-time advance 0 1 1 Each bit is transmitted with 2 bit-time advance.
When IMTD = 0 (bit of SMCR), DEL = 0 is not taken into account by the circuit. 1/2 bit time 244ns if TDM at 2048 kHz, 1/2 bit time 122ns if TDM at 4096 kHz. OMV (i) : Output Multiplex Validated 0/7 OMVi =1, condition to have DOUTi pin active (0 i 7). OMVi =0, DOUTi pin is High Impedance continuously (0 i 7).
N.B. If DIN4 and DIN5 are GCI Multiplexes : then ST(4)1 = ST(4)0 = 0 and ST(5)1 = ST(5)0 = 0 normally.
VIII.7 - Switching Matrix Configuration Register - SMCR (0C)H
bit15 SW1 SW0 M1 M0 bit8 bit7 ME SGC SAV SGV TS1 TS0 bit 0 IMTD DR64 DR44 DR24 DR04 AISD After reset (0000)H
IMTD
: Increased Minimum Throughput Delay When SI = 0 (bit of CMDR, variable delay mode) : IMTD = 1, the minimum delay through the matrix memory isthree time slots whateverthe selected TDM output. IMTD = 0, the minimum delay through the matrix memory is two time slots whatever the selected TDM output. When IMTD = 0, the input TDMs cannot be delayed versus the frame synchronization (Use of IMCR is limited) and the output TDMs cannot be advanced versus the frame synchronization.(Use of OMCR is limited).
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STLC5465B
VIII - INTERNAL REGISTERS (continued) TS0 : Tristate 0 TS0 = 1, the DOUT0/3 and DOUT6/7 pins are tristate : "0" is at low impedance, "1" is at low impedance and the third state is high impedance. TS0 = 0, the DOUT0/3 and DOUT6/7 pins are open drain : "0" is at low impedance, "1" is at high impedance. TS1 : Tristate 1 TS1 = 1, the DOUT4/5 pins are tristate : "0" is at low impedance, "1" is at low impedance and the third state is high impedance. TS1 = 0, the DOUT4/5 pins are open drain : "0" is at low impedance, "1" is at high impedance. SGV : Pseudo Random Sequence Generator Validated SGV = 1,PRS Generator is validated.The Pseudo Random Sequence is transmitted during the related time slot(s). SGV = 0, PRS Generator is reset."0" are transmitted during the related time slot. SAV : Pseudo Random Sequence analyzer Validated SAV = 1, PRS analyzer is validated. SAV = 0, PRS analyzer is reset. SGC : Pseudo Random Sequence Generator Corrupted When SGC bit goes from 0 to 1, one bit of sequence transmitted is corrupted. When the corrupted bit has been transmitted, SGC bit goes from 1 to 0 automatically. ME : MESSAGE ENABLE ME = 1 The contents of Connection Memory is output on DOUT0/7 continuously. ME = 0 The contents of Connection Memory acts as an address for the Data Memory. AISD : Alarm Indication Signal Detection. AISD = 1, the Alarm Indication Signal detection is validated. Sixteen independent detections are performed for sixteen hyperchannels. The contents of any input hyperchannel (B1, B2, D) switched (in transparent mode or not) on GCI channels is analysed independently. For each GCI channel, the 16bits of B1 and B2 are checked together; when all "one" has been detected during 30 milliseconds, a status is stored in the Command/ Indicate interrupt queue and an interrupt is generatedif not masked (like the receptionof primitive from GCI multiplexes). See "RECEIVE Command/Indicate INTERRUPT" on page 97. AISD=0, the Alarm Indication Signal detection for 16 hyperchannelsis not validated. DR04 : Data Rate of TDM0 is at 4Mb/s. Case:M1=M0=0 DR04 = 1, the signal received from DIN0 pin and the signal delivered by Dout0 pin are at 4Mb/s. DIN1 pin and DOUT1 pin are ignored. The Time Division Multiplex 0 is constituted by 64 timeslots numbered from 0 to 63. DR04 = 0, the signals received from DIN0/1 pins and the signals delivered by Dout0/1 pins are at 2Mb/s. DR24 : Data Rate of TDM2 is at 4Mb/s.Case:M1=M0=0 R24 = 1, the signal received from DIN2 pin and the signal delivered by Dout2 pin are at 4Mb/s. DIN3 pin and DOUT3 pin are ignored. The Time Division Multiplex 2 is constituted by 64 timeslots numbered from 0 to 63. DR24 = 0, the signals received from DIN2/3 pins and the signals delivered by Dout2/3 pins are at 2Mb/s. DR44 : Data Rate of TDM4 is at 4Mb/s.Case: M1=M0=0 DR44 = 1, the signal received from DIN4 pin and the signal delivered by Dout4 pin are at 4Mb/s. DIN5 pin and DOUT5 pin are ignored. TDM4/5 cannot be GCI multiplexes. The Time Division Multiplex 4 is constituted by 64 timeslots numbered from 0 to 63. DR44 = 0, the signals received from DIN4/5 pins and the signals delivered by Dout4/5 pins are at 2Mb/s.
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STLC5465B
VIII - INTERNAL REGISTERS (continued) DR64 : Data Rate of TDM6 is at 4Mb/s.Case:M1=M0=0 DR64 = 1, the signal received from DIN6 pin and the signal delivered by Dout6 pin are at 4Mb/s. DIN7 pin and DOUT7 pin are ignored. The Switching Matrix cannot be used to switch the channels to/from the HDLC controllers but the RX HDLC controller can be connected to DIN8 and the TX HDLC controllercan be connected to CB pin. The Time Division Multiplex 6 is constituted by 64 timeslots numbered from 0 to 63. DR64 = 0, the signals received from DIN6/7 pins and the signals delivered by Dout6/7 pins are at 2M b/s. M1/0 : Data Rate of TDM0/8; these two bits indicate the data rate of height TimeDivision Multiplexes TDM0/7relativeto DIN0/7 and DOUT0/7. The table below shows the different data rates with the clock frequency defined by HCL bit (General Configuration Register).
M1 M0 Data Rate of TDM0/7 in Kbit/s CLOCKA/B signal frequency HCL = 0 0 0 1 1 0 1 0 1 2048 (or 4096 in accordance with DR0x4) 1536 (or 3072 in accordance with DR0x4) Reserved Reserved 4096KHz 3072KHz HCL = 1 8192KHz 6144KHz
SW
: Switching at 32 Kbit/s for the TDM0 (DIN0/DOUT0) SW0=1 DIN0 can receive 64 channels at 32 Kbit/s if Data Rate of TDM0 is at 2048 Kbit/s. DOUT0 can deliver 64 channels at 32 Kbit/s. DIN2/DOUT2 are not available. DIN2 is used to receive internally TDM0 (DIN0) 4 bit-times shifted DOUT2 is used to multiplex internally TDM2 and TDM4. Downstream switching at 32 kb/s on page 22. : SW1: Switching at 32 Kbit/s for the TDM1 (DIN1/DOUT1) SW1=1 DIN1 can receive 64 channels at 32 Kbit/s if Data Rate of TDM1is at 2048 Kbit/s.DOUT0 can deliver 64 channels at 32 Kbit/s. DIN3/DOUT3 are not available. DIN3 is used to receive internally TDM1(DIN1) and to shift it (4 bit-times)DOUT3 is used to multiplex internally TDM3 and TDM5. Downstream switching at 32 kb/s on page 22. SW1=0 DIN0 receive 32 (or 24) channels at 64 Kbit/s or 64 (or 48) channels at 64 Kbit/s depending on DR04 bit.
SW1
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VIII - INTERNAL REGISTERS (continued) VIII.8 - Connection Memory Data Register - CMDR (0E)H
CONTROL REGISTER (CTLR) bit15 SCR PS PRSA S1 S0 OTSV LOOP bit8 SI bit7 IM2 IM1 IM0 SOURCE REGISTER (SRCR) bit 0 ITS 4 ITS 3 ITS 2 ITS 1 ITS 0
After reset (0000)H
This 16 bit register is constituted by two registers : SOURCE REGISTER (SRCR) and CONTROL REGISTER (CTLR) SOURCE REGISTER (SRCR) has two use modes depending on CM (bit of CMAR). CM = 1, access to connection memory (read or write) - PRSG = 0, ITS 0/4 and IM0/2 bits are defined hereafter : ITS 0/4 : Input time slot 0/4 define ITSx with : 0 x 31; IM0/2 : Input Time Division Multiplex 0/2 define ITDMp with : 0 p 7. - PRSG = 1, the Pseudo Random Sequence Generator is validated, SRCR is not significant. CM = 0, access to data memory (read only). SRC is the data register of the data memory. CONTROL REGISTER (CTLR) defines each Output Time Slot OTSy of each Output Time Division Multiplex OTDMq : SI : SEQUENCE INTEGRITY SI = 1, the delay is always : (31 - ITSx) + 32 + OTSy. SI = 0, the delay is minimum to pass through the data memory. LOOP : LOOPBACK per channel relevant if a bidirectional connection has been established. LOOP = 1, OTSy, OTDMq is taken into account instead of ITSy, ITDMq. OTSV = 1, transparent Mode LOOPBACK. OTSV = 0, not Transparent Mode LOOPBACK. OTSV : OUTPUT TIME SLOT VALIDATED OTSV = 1, OTSy OTDMq is enabled. OTSV = 0, OTSy OTDMq is High Impedance. (OTSy : OutputTime slot with 0 y 31; OTDMq : OutputTime Division Multiplex with 0 q 7). S1/S0 : SOURCE 1/0
S1 0 0 1 1 S0 0 1 0 1 Source for each timeslot of DOUT0/7 Data Memory (Normal case) Connection Memory D channels from/to GCI multiplexes (See note and table hereafter) Pseudo Random Sequence Generator delivers Hyperchannel at n x 64Kb/s is possible.
Note: Connection When the source of D channels is selected (GCI channelsdefined by ITS 1/0) and when the destination is selected (Output timeslot defined by OTS 0/4; output TDM defined by OM 0/2) the upstream connection is set up; the downstream connection (reverse direction TDM to GCI) is set up automatically if ITS 2 bit is at 1. So BID, bit of CMAR must be written at"0". Release Remember: write S1=1, S0=0 and ITS 2 bit = 0 to release the downstream connection; the upstream connection is released when the source changes.
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VIII - INTERNAL REGISTERS (continued) TABLE: SWITCHING AT 16Kb/s WHEN ITS3 = 0
S1 S0 ITS 3 ITS 2 ITS 1 ITS 0 Upstream Source: D channels of one of 16 GCI channels Destination: two bits of one TDM The contents of D channels of GCI 0 /3 of multiplex DIN4 are transferred into the output timeslot of one TDM defined by the destination register (CMAR). D channel of GCI 0 in bit 1/2 D channel of GCI 1 in bit 3/4 D channel of GCI 2 in bit 5/6 D channel of GCI 3 in bit 7/8 The contents of D channels of GCI 4/7 of multiplex DIN4 are transferred into the output timeslot of one TDM defined by the destination register (CMAR). D channel of GCI 4 in bit 1/2 D channel of GCI 5 in bit 3/4 D channel of GCI 6 in bit 5/6 D channel of GCI 7 in bit 7/8 The contents of D channels of GCI 0 /3 of multiplex DIN5 are transferred into the output timeslot of one TDM defined by the destination register (CMAR). D channel of GCI 0 in bit 1/2 D channel of GCI 1 in bit 3/4 D channel of GCI 2 in bit 5/6 D channel of GCI 3 in bit 7/8 The contents of D channels of GCI 4/7 of multiplex DIN5 are transferred into the output timeslot of one TDM defined by the destination register (CMAR). D channel of GCI 4 in bit 1/2 D channel of GCI 5 in bit 3/4 D channel of GCI 6 in bit 5/6 D channel of GCI 7 in bit 7/8 Downstream Source: two bits of one TDM Destination: D channels of one of 16 GCI channels The contents of the input timeslot (same number as the number of the output timeslot) is transferred in D channel of GCI 0/3 of multiplex DOUT4 bit 1/2 in D channel of GCI 0 bit 3/4 in D channel of GCI 1 bit 5/6 in D channel of GCI 2 bit 7/8 in D channel of GCI 3 The contents of the input timeslot (same number as the number of the output timeslot) is transferred in D channel of GCI 4/7 of multiplex DOUT4. bit 1/2 in D channel of GCI 4 bit 3/4 in D channel of GCI 5 bit 5/6 in D channel of GCI 6 bit 7/8 in D channel of GCI 7 The contents of the input timeslot (same number as the number of the output timeslot) is transferred in D channel of GCI 0/3 of multiplex DOUT5. bit 1/2 in D channel of GCI 0 bit 3/4 in D channel of GCI 1 bit 5/6 in D channel of GCI 2 bit 7/8 in D channel of GCI 3 The contents of the input timeslot (same number as the number of the output timeslot) is transferred in D channel of GCI 4/7 of multiplex DOUT5. bit 1/2 in D channel of GCI 4 bit 3/4 in D channel of GCI 5 bit 5/6 in D channel of GCI6 bit 7/8 in D channel of GCI 7
0
0
0
1
1
0
0
1
1
0
1
1
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VIII - INTERNAL REGISTERS (continued) TABLE: SWITCHING AT 16KB/S when ITS3 =1
S1 S0 ITS 3 ITS 2 ITS 1 ITS 0 Upstream Source: D channels of one of 16 GCI channels Destination: two bits of one TDM The contents of D channels of GCI 0 /3 of multiplex DIN4 are transferred into the output timeslot of one TDM defined by the destination register (CMAR). D channel of GCI 0 in bit 7/8 D channel of GCI 1 in bit 5/6 D channel of GCI 2 in bit 3/4 D channel of GCI 3 in bit 1/2 The contents of D channels of GCI 4/7 of multiplex DIN4 are transferred into the output timeslot of one TDM defined by the destination register (CMAR). D channel of GCI 4 in bit 7/8 D channel of GCI 5 in bit 5/6 D channel of GCI 6 in bit 3/4 D channel of GCI 7 in bit 1/2 The contents of D channels of GCI 0 /3 of multiplex DIN5 are transferred into the output timeslot of one TDM defined by the destination register (CMAR). D channel of GCI 0 in bit 7/8 D channel of GCI 1 in bit 5/6 D channel of GCI 2 in bit 3/4 D channel of GCI 3 in bit 1/2 The contents of D channels of GCI 4/7 of multiplex DIN5 are transferred into the output timeslot of one TDM defined by the destination register (CMAR). D channel of GCI 4 in bit 7/8 D channel of GCI 5 in bit 5/6 D channel of GCI 6 in bit 3/4 D channel of GCI 7 in bit 1/2 Downstream Source: two bits of one TDM Destination: D channels of one of 16 GCI channels The contents of the input timeslot (same number as the number of the output timeslot) is transferred in D channel of GCI 0/3 of multiplex DOUT4 bit 7/8 in D channel of GCI 0 bit 5/6 in D channel of GCI 1 bit 3/4 in D channel of GCI 2 bit 1/2 in D channel of GCI 3 The contents of the input timeslot (same number as the number of the output timeslot) is transferred in D channel of GCI 4/7 of multiplex DOUT4. bit 7/8 in D channel of GCI 4 bit 5/6 in D channel of GCI 5 bit 3/4 in D channel of GCI 6 bit 1/2 in D channel of GCI 7 The contents of the input timeslot (same number as the number of the output timeslot) is transferred in D channel of GCI 0/3 of multiplex DOUT5. bit 7/8 in D channel of GCI 0 bit 5/6 in D channel of GCI 1 bit 3/4 in D channel of GCI 2 bit 1/2 in D channel of GCI 3 The contents of the input timeslot (same number as the number of the output timeslot) is transferred in D channel of GCI 4/7 of multiplex DOUT5. bit 7/8 in D channel of GCI 4 bit 5/6 in D channel of GCI 5 bit 3/4 in D channel of GCI 6 bit 1/2 in D channel of GCI 7
0
0
0
1
1
0
1
1
1
0
1
1
PRSA : Pseudo Random Sequence analyzer If PRSA = 1, PRS analyzer is enabled during OTSy OTDMq and receives data : INS = 0, data comes from Data Memory. INS = 1 AND PRSG=1, Data comes from PRS Generator (Test Mode). If PRSA = 0, PRS analyzer is disabled during OTSy OTDMq. PS : Programmable Synchronization If PS = 1, Programmable Synchronization Signal Pin is at "1" during the bit time defined by OTSy and OTDMq. For OTSy and OTDMq with y = q = 0, PSS pin is at "1" during the first bit of the frame defined by the Frame synchronization Signal (FS). If PS = 0, PSS Pin is at "0" during the bit time defined by OTSy and OTDMq.
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VIII - INTERNAL REGISTERS (continued) VIII.9 - Connection Memory Address Register - CMAR (10)H
ACCESS MODE REGISTER (AMR) bit15 Nu Nu TC CACL CAC BID CM bit8 bit7 OM1 READ OM2 DESTINATION REGISTER (DSTR) bit 0 OM0 OTS4 OTS3 OTS2 OTS1 OTS0
After reset (0800)H
This 16 bit registeris constitutedby two registers: DESTINATIONREGISTER (DSTR) and ACCESS MODE REGISTER (AMR) respectively 8 bits and 6 bits. DESTINATION REGISTER (DSTR) When DSTR Register is written by the microprocessor, a memory access is launched. DSTR has two use modes depending on CM (bit of CMAR). CM = 1, access to connection memory (read or write) ; OTS 0/4 : Output time slot 0/4 define OTSy with : 0 y 31, OM0/2 : Output Time Division Multiplex 0/2 define OTDMq with : 0 q 7. See table hereafter when DR04, DR24, DR44 and/or DR64 are at "1"; the bits of SMCR define the TDMs at 4 Mbit/s. The IM2/1 bits of Source Register (SRCR of CMDR) indicate the DIN pin number and the OM2/1 bits of Destination Register (DSTR of CMAR) indicate the Dout pin number.
IM2 (bit7) 0 0 1 1 IM1 (bit6) 0 1 0 1 DIN pin DIN0 DIN2 DIN4 DIN6 OM2 (bit7) 0 0 1 1 OM1(bit6) 0 1 0 1 DOUT pin DOUT0 DOUT2 DOUT4 DOUT6
The ITS4/0 and IM0 bits of Source Register (SRCR of CMDR) indicate the input timeslot number. (IM0 bit is the Least Significant Bit; it indicates either even timeslot or odd timeslot.
ITS4 (bit4) 0 0 0 0 ITS3 (bit3) 0 0 0 0 ITS2 (bit2) 0 0 0 0 = 1 1 1 1 1 1 ITS1 (bit1) 0 0 0 0 ITS0 (bit0) 0 0 1 1 IMO (bit5) 0 1 0 1 Input timeslot number 0 1 2 3 = 63
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VIII - INTERNAL REGISTERS (continued) The OTS4/0 and OM0 bits of Destination Register (DSTR of CMAR) indicate the output timeslot number. (OM0 bit is the Least Significant Bit; it indicates either even timeslot or odd timeslot
OTS4 (bit4) 0 0 0 0 1 OTS3 (bit3) 0 0 0 0 1 OTS2 (bit2) 0 0 0 0 = 1 1 1 1 OTS1 (bit1) 0 0 0 0 OTS0 (bit0) 0 0 1 1 OMO (bit5) 0 1 0 1 Output timeslot number 0 1 2 3 = 63
Nota Bene: - CLOCK A/B is at 4 or at 8 MHz in accordance with HCL bit of General Configuration Register GCR (02). HCL=1, bit clock frequency is at 8 192 KHz. For a TDM at 4 Mbit/s or 2Mbit/s, each received bit is sampled at 3/4 bit-time. HCL=0, bit clock frequency is at 4 096 KHz For a TDM at 4 Mbit/s, each received bit is sampled at half bit-time. For a TDM at 2 Mbit/s, each received bit is sampled at 3/4 bit-time. The definition of IMCRO/1, OMCRO/1 are kept with bit time = 244 ns Remarks: - OM0, bit5 of DSTR indicates either even TDM or odd TDM if TDM at 2 Mb/s. - OM0, bit5 of DSTR indicates either even Output timeslot or odd Output timeslot if TDM at 4 Mb/s. - IM0, bit5 of SRCR indicates either even TDM or odd TDM if TDM at 2 Mb/s. - IM0, bit5 of SRCR indicates either even Output timeslot or odd Output timeslot if TDM at 4 Mb/s. - CAC = CACL = 0, DSTR is the Address Register of the Connection Memory; - CAC or CACL = 1, DSTR is used to indicate the current address for the Connection Memory ; its contents is assigned to the outputs. CM = 0, access to data memory (read only) ; - DSTR is the Address Register of the Data Memory; its contents is assigned to the inputs. ACCESS MODE REGISTER (AMR) READ : READ MEMORY READ = 1, Read Connection Memory (or Data Memory in accordance with CM). READ = 0, Write Connection Memory. CM : CONNECTION MEMORY CM = 1, Write or Read Connection Memory in accordance with READ. CM = 0, Read only Data Memory (READ = 0 has no effect). BID : BIDIRECTIONAL CONNECTION BID = 1; Two connections are set up: ITSx ITDMp ------> OTSy OTDMq (LOOP of CMDR Register is taken into account) and ITSy ITDMq ------> OTSx OTDMp (LOOP of CMDR Register is not taken into account). BID = 0; One connection is set up: ITSx ITDMp ------> OTSy OTDMq only. CAC : CYCLICAL ACCESS CAC = 1 (BID is ignored) if Write Connection Memory, an automatic data write from Connection Memory Data Register (CMDR) up to 256 locations of Connection Memory occurs. The first address is indicated by the register DSTR, the last is (FF)H. if Read Connection Memory, an automatic transfer of data from the location indicated by the register (DSTR) into Connection Memory Data Register (CMDR) after reading by the microprocessor occurs. The last location is (FF)H. CAC = 0, Write and Read Connection Memory in the normal way.
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VIII - INTERNAL REGISTERS (continued) CACL : CYCLICAL ACCESS LIMITED CACL = 1 (BID is ignored) If Write Connection Memory, an automatic data write from Connection Memory Data Register (CMDR) up to 32 locations of Connection Memory occurs. The first location is indicated by OTS 0/4bits of the register (DSTR) related to OTDMq as defined by OM0/2 occurs. The last location is q +1 F(H). If Read Connection Memory, an automatic transfer of data from Connection Memory into Connection Memory Data Register (CMDR) after reading this last by the microprocessor occurs.The first location is indicated by OTS 0/4 bits of the register (DSTR) related to OTDMq as defined by OM0/2. The last location is q +1 F(H). CACL = 0, Write and Read Connection Memory in the normal way. TC : Transparent Connection TC = 1, (BID is ignored), if READ = 0 : CAC = 0 and CACL = 0. The DSTR bits are taken into account instead of SRCR bits. SRCR bits are ignored (Destination and Source are identical). The contents of Input time slot i - Input multiplex j is switched into Output time slot i - Output multiplex j. CAC = 0 and CACL = 1. Up to 32 "Transparent Connections" are set up. CAC = 1 and CACL = 0. Up to 256 "Transparent Connections" are set up. TC = 0, Write and Read Connection Memory are in accordance with BID. VIII.10 - Sequence Fault Counter Register - SFCR (12)H
bit15 F15 F14 F13 F12 F11 F10 F9 bit8 F8 bit7 F7 F6 F5 F4 F3 F2 F1 bit 0 F0
After reset (0000)H
When this register is read by the microprocessor, this register is reset (0000)H. F0/15 : FAULT0/15 Number of faults detected by the Pseudo Random Sequence analyzer if the analyzer has been validated and has recovered the receive sequence. When the Fault Counter Register reaches (00FF)H it stays at its maximum value. NB. As the SFCR is reset after reading, a 8-bit microprocessor must read the LSB that will represent the number of faults between 0 and 255. To avoid overflow escape notice, it is necessaryto start counting at FF00h, by writing this value in SFCR before launching PRSA. If there are more than FFh errors, the SFCO interrupt bit (see interrupt register IR -38H address) will signal that the fault count register has reached the value FFFFh (because of the number of faults exceeded 255). VIII.11 - Time Slot Assigner Address Register - TAAR (14)H
bit15 TS4 TS3 TS2 TS1 TS0 READ Nu bit8 HDI bit7 r e s e r v e bit 0 d
After reset (0100)H
READ : READ MEMORY READ = 1, Read Time slot Assigner Memory. READ = 0, Write Time slot Assigner Memory. TS0/4 : TIME SLOTS0/4 These five bits define one of 32 time slots in which a channel is set-up or not.
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VIII - INTERNAL REGISTERS (continued) HDI : HDLC INIT HDI = 1, TSA Memory, Tx HDLC, Tx DMA, Rx HDLC, Rx DMA and GCI controllers are reset within 250ms. An automate writes data from Time slot Assigner Data Register (TADR) (except CH0/4 bits) into each TSA Memory location. If the microprocessor reads Time slot Assigner Memory after HDLC INIT, CH0/4 bits of Time slot Assigner Data Register are identical to TS0/4 bits of Time slot Assigner Address Register. HDI = 0, Normal state. After software reset (bit 2 of IDCR Register) or pin reset the automate above-mentioned is working. The automate is stopped when the microprocessor writes TAAR Register with HDI = 0.
N.B.
VIII.12 - Time Slot Assigner Data Register - TADR (16)H
bit15 V11 V10 V9 V8 V7 V6 V5 bit8 V4 bit7 V3 V2 V1 CH4 CH3 CH2 CH1 bit 0 CH0
After reset (0000)H
CH0/4 : CHANNEL0/4 These five bits define one of 32 channels associated to TIME SLOT defined by the previous Register (TAAR). V1/8 : VALIDATION The logical channel CHx is constituted by each subchannel 1 to 8 and validated by V1/8 bit at 1 respectively. V1 to V8 at 0: the subchannels are ignored V1 at 1: the first bit of the current time slot is taken into account in reception the first bit received and in transmission the first bit transmitted. V8 at 1: the last bit of the current time slot is taken into account in reception the last bit received and in transmission the last bit transmitted in transmission. V9 : VALIDATION SUBCHANNEL V 9 = 1, each V1/8 bit is taken into account once every 250ms. In transmit direction, data is transmitted consecutively during the time slot of the current frame and during the same time slot of the next frame.Id est.: the same data is transmitted in two consecutive frames. In receive direction, HDLC controller fetches data during the time slot of the current frame and ignores data during the same time slot of the next frame. V 9 = 0, each V1/8 bit is taken into account once every 125ms. V10 : DIRECT MHDLC ACCESS If V10 = 1, the Rx HDLC Controller receives data issued from DIN8 input during the current time slot (bits validated by V1/8) and DOUT6 output transmits data issued from the Tx HDLC Controller. If V10 = 0, the Rx HDLC Controller receives data issued from the matrix output 7 during the current time slot ; DOUT6 output delivers data issued from the matrix output 6 during the same current time slot. N.B : If D7 = 1, (see "General Configuration Register GCR (02)H") the Tx HDLC controller is connected to matrix input 7 continuously so the HDLC frames can be sent to any DOUT (i.e. DOUT0 to DOUT7). V11 : VALIDATION of CB pin This bit is not taken into account if CSMA = 1 (HDLC Transmit Command Register). if CSMA = 0 : V11 = 1, Contention Bus pin is validated and Echo pin (which is an input) is not taken into account. V11 = 0, ContentionBus pin is high impedance during the current time slot (This pin is an open drain output).
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VIII - INTERNAL REGISTERS (continued) VIII.13 - HDLC Transmit Command Register - HTCR (18)H
bit15 CH4 CH3 CH2 CH1 CH0 READ Nu bit8 CF bit7 PEN CSMA NCRC F P1 P0 C1 bit 0 C0
After reset (0000)H
READ : READ COMMAND MEMORY READ = 1, READ COMMAND MEMORY. READ = 0, WRITE COMMAND MEMORY. CH0/4 : These five bits define one of 32 channels. C1/C0 : COMMAND BITS
C1 0 C0 0 Commands Bits ABORT ; if this command occurs during the current frame, HDLC Controller transmits seven "1" immediately, afterwards HDLC Controller transmits "1" or flag in accordance with F bit, generates an interrupt and waits new command such as START orn CONTINUE. If this command occurs after transmitting a frame, HDLC Controller generates an interrupt and waits a new command such as START or CONTINUE. START ; Tx DMA Controller is now going to transfer first frame from buffer related to initial descriptor. The initial descriptor address is provided by the Initiate Block located in external memory. CONTINUE ; Tx DMA Controller is now going to transfer next frame from buffer related to next descriptor. The next descriptor address is provided by the previous descriptor from which the related frame had been already transmitted. HALT ; after transmitting frame, HDLC Controller transmits "1" or flag in accordance with F bit, generates an interrupt and is waiting new command such as START or CONTINUE.
0
1
1
0
1
1
P0/1
: PROTOCOL BITS
P1 0 0 1 1 P0 0 1 0 1 HDLC Transparent Mode 1 (per byte) ; the fill character defined in FCR Register is taken into account. Transparent Mode 2 (per byte) ; the fill character defined in FCR Register is not taken into account. Reserved Transmission Mode
: Flag F = 1 ; flags are transmitted between closing flag of current frame and opening flag of next frame. F = 0 ; "1" are transmitted between closing flag of current frame and opening flag of next frame. NCRC : CRC NOT TRANSMITTED NCRC = 1, the CRC is not transmitted at the end of the frame. NCR C =0, the CRC is transmitted at the end of the frame. CSMA : Carrier Sense Multiple Access with Contention Resolution CSMA = 1, CB output and the Echo Bit are taken into account during this channel transmission by the Tx HDLC. CSMA = 0, CB output and the Echo Bit are defined by V11 (see " Time slot Assigner Data Register TADR (16)H").
F
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VIII - INTERNAL REGISTERS (continued) PEN : CSMA PENALTY significant if CSMA = 1 PEN = 1, the penalty value is 1 ; a transmitter which has transmitted a frame correctly will count (PRI +1) logic one received from Echo pin before transmitting next frame. (PRI, priority class 8 or 10 given by the buffer descriptor related to the frame. PEN = 0, the penalty value is 2 ; a transmitter which has transmitted a frame correctly will count (PRI +2) logic one received from Echo pin before transmitting next frame. (PRI, priority class 8 or 10 given by the transmit descriptor related to the frame). : Common flag CF = 1, the closing flag of previous frame and opening flag of next frame are identical if the next frame is ready to be transmitted. CF = 0, the closing flag of previous frame and opening flag of next frame are distinct.
CF
VIII.14 - HDLC Receive Command Register - HRCR (1A)H
bit15 CH4 CH3 CH2 CH1 CH0 READ AR21 bit8 AR20 bit7 AR11 AR10 CRC FM P1 P0 C1 bit 0 C0
After reset (0000)H
READ : READ COMMAND MEMORY READ = 1, READ COMMAND MEMORY. READ = 0, WRITE COMMAND MEMORY. CH0/4 : These five bits define one of 32 channels. C1/C0 : COMMAND
C1 0 C0 0 Commands Bits ABORT ; if this command occurs during receiving a current frame, HDLC Controller stops the reception, generates an interrupt and waits new command such as START orn CONTINUE. If this command occurs after receiving a frame, HDLC Controller generates an interrupt and waits a new command such as START or CONTINUE. START ; Rx DMA Controller is now going to transfer first frame into buffer related to the initial descriptor. The initial descriptor address is provided by the Initiate Block located in external memory. CONTINUE ; Rx DMA Controller is now going to transfer next frame into buffer related to next descriptor. The next descriptor address is provided by the previous descriptor from which the related frame had been already received. HALT ; after receiving frame, HDLC Controller stops the reception, generates an interrupt and waits a new command such as START or CONTINUE.
0
1
1
0
1
1
P0/1
: PROTOCOL BITS
P1 0 0 1 1 P0 0 1 0 1 HDLC Transparent Mode 1 (per byte) ; the fill character defined in FCR Register is taken into account. Transparent Mode 2 (per byte) ; the fill character defined in FCR Register is not taken into account. Reserved Transmission Mode
FM
CRC
: Flag Monitoring. This bit is a status bit read by the microprocessor. FM=1: HDLC Controller is receiving a frame or HDLC Controller has just received one flag. FM is put to 0 by the microprocessor. : CRC stored in external memory CRC = 1, the CRC is stored at the end of the frame in external memory. CRC = 0, the CRC is not stored into external memory.
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VIII - INTERNAL REGISTERS (continued) AR10 : Address Recognition10 AR10 = 1, First byte after opening flag of received frame is compared to AF0/7 bits of AFRDR. If the first byte received and AF0/7 bits are not identical the frame is ignored. AR10 = 0, First byte after opening flag of received frame is not compared to AF0/7 bits of AFRDR Register. : Address Recognition 11 AR11 = 1, First byte after opening flag of received frame is compared to all "1"s.If the first byte received is not all "1"s the frame is ignored. AR11 = 0, First byte after opening flag of received frame is not compared to all "1"s. : Address Recognition 20 AR20 = 1, Second byte after opening flag of receivedframe is comparedto AF8/15bits of AFRDR Register. If the second byte received and AF8/15 bits are not identical the frame is ignored. AR20 = 0, Second byte after opening flag of received frame is not compared to AF8/15 bits of AFRDR Register. : Address Recognition 21 AR21 = 1, Second byte after opening flag of received frame is compared to all "1"s. If the Second byte received is not all "1"s the frame is ignored. AR21 = 0, Second byte after opening flag of received frame is not compared to all "1"s.
Second Byte First Byte AR21 AR20 AR11 AR10 0 0 0 0 0 0 0 1 0 0 1 0 0 0 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 1 0 1 Conditions to Receive a Frame Each frame is received without condition. Only value of the first received byte must be equal to that of AF0/7 bits. Only value of the first received byte must be equal to all "1"s. The value of the first received byte must be equal either to that of AF0/7 or to all "1"s. Only value of the second received byte must be equal to that of AF8/15 bits. The value of the first received byte must be equal to that of AF0/7 bits and the value of the second received byte must be equal to that of AF8/15 bits. The value of first received byte is must be equal to all "1"s and the value of second received byte must be equal to that of AF8/15 bits. The value of the first received byte must be equal either to that of AF0/7 or to all "1"s and the value of the second received byte must be equal to that of AF8/15 bits. Only the value of the second received byte must be equal to all "1"s. The value of the first received byte must be equal to that of AF0/7 bits and the value of the second received byte must be equal to all "1"s. The value of the first received byte must be equal to all "1"s and the value of the second received byte must be equal to "1" also. The value of the first received byte must be equal either to that of AF0/7 or to "1" and the value of the second received byte must be equal to all "1"s. The value of the second received byte must be equal either to that of AF8/15 or to all "1"s. The value of the first received byte must be equal to that of AF0/7 bits and the value of the second received byte must be equal either to that of AF8/15 or to all "1"s. The value of the first received byte must be equal to "1" and the value of the second received byte must be equal either to that of AF8/15 or to all "1"s. The value of the first received byte must be equal either to that of AF0/7 or to "1" and the value of the second received byte must be equal either to that of AF8/15 or to all "1"s.
AR11
AR20
AR21
1 1 1 1 1 1
0 0 0 0 1 1
0 0 1 1 0 0
0 1 0 1 0 1
1 1
1 1
1 1
0 1
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VIII - INTERNAL REGISTERS (continued) VIII.15 - Address Field Recognition Address Register - AFRAR (1C)H
bit15 CH4 CH3 CH2 CH1 CHO READ AMM bit8 Nu bit7 r e s e r v e bit 0 d
After reset (0000)H
The write operation is lauched when AFRAR is written by the microprocessor. AMM : Access to Mask Memory. AMM=1, Access to Address Field Recognition Mask Memory. AMM=0, Access to Address Field Recognition Memory. READ : READ ADDRESS FIELD RECOGNITION MEMORY READ=1, READ AFR MEMORY. READ=0, WRITE AFR MEMORY. CH0/4 : These five bits define one of 32 channels in reception VIII.16 - Address Field Recognition Data Register - AFRDR (1E)H
bit15
AF15/ AF14/ AF13/ AF12/ AF11/ AF10/ AF9/ AFM15 AFM14 AFM13 AFM12 AFM11 AFM10 AFM9
bit8
AF8/ AFM8
bit7
AF7/ AFM7 AF6/ AFM6 AF5/ AFM5 AF4/ AFM4 AF3/ AFM3 AF2/ AFM2 AF1/ AFM1
bit 0
AF0/ AFMO
After reset (0001)H
AF0/15 : ADDRESS FIELD BITS AF0/7 ; First byte received; AF8/15: Second byte received. These two bytes are stored into Address Field Recognition Memory when AFRAR is written by the microprocessor. AFM0/ ADDRESS FIELD BIT MASK0/15 if AMM=1 (AMM bit of AFRAR) 15: AMF0/7. When AR10=1 (See HRCR) each bit of the first received byte is compared respectively to AFx bit if AFMx=0. In case of mismatching, the received frame is ignored. If AFMx=1, no comparison between AFx and the corresponding received bit. AMF8/15. When AR20=1 (See HRCR) each bit of the second received byte is compared respectively to AFy bit if AFMy=0. In case of mismatching, the received frame is ignored. If AFMy=1, no comparison between AFy and the corresponding received bit. These two bytes are stored into Address Field Recognition Mask Memory when AFRAR is written by the microprocessor (AMM=1). VIII.17 - Fill Character Register - FCR (20)H
bit15 r e s e r v e bit8 d bit7 FC7 FC6 FC5 FC4 FC3 FC2 FC1 bit 0 FC0
After reset (0000)H
FC0/7 : FILL CHARACTER (eight bits) In TransparentMode M1, two messages are separatedby FILL CHARACTERS and the detection of one FILL CHARACTER marks the end of a message. VIII.18 - GCI Channels Definition Register 0 - GCIR0 (22)H The definitions of x and y indices are the same for GCIR0, GCIR1, GCIR2, GCIR3 : - 0 x 7, 1 of 8 GCI CHANNELS belonging to the same multiplex TDM4 or TDM5 - y = 0, TDM4 is selected - y = 1, TDM5 is selected.
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VIII - INTERNAL REGISTERS (continued)
bit15 TDM5 GCI CHANNEL 1 After reset (0000)H TDM4 bit8 bit7 TDM5 GCI CHANNEL 0 TDM4 bit 0 ANA11 VCI11 V*11 VM11 ANA10 VCI10 V*10 VM10 ANA01 VCI01 V*01 VM01 ANA00 VCI00 V*00 VM00
VMxy : VALIDATION of MONITOR CHANNELx, MULTIPLEX y : When this bit is at 1, monitor channel xy is validated. When this bit is at 0, monitor channel xy is not validated. On line to reset (if necessary)one MON channel which had been selected previouslyVMxy must be put at 0 during 125ms before reselecting this channel. Deselecting one MON channel during 125ms resets this MON channel. V*xy : VALIDATION of V Starx, MULTIPLEX y When this bit is at 1, V Star protocol is validated if VMxy=1. When this bit is at 0, GCI Monitor protocol is validated if VMxy=1. VCxy : VALIDATION of Command/Indicate CHANNEL x, MULTIPLEXy When this bit is at 1, Command/Indicate channelxy is validated. When this bit is at 0, Command/Indicate channelxy is not validated. It is necessary to let VCxy at "0" during 125ms to initiate the Command/Indicate channel. ANAxy : ANALOG APPLICATION When this bit is at 1, Primitive has 6 bits if C/Ixy is validated. When this bit is at 0, Primitive has 4 bits if C/Ixy is validated. VIII.19 - GCI Channels Definition Register 1 - GCIR1 (24)H
bit15 TDM5 GCI CHANNEL 3 After reset (0000)H TDM4 bit8 bit7 TDM5 GCI CHANNEL 2 TDM4 bit 0 ANA31 VCI31 V*31 VM31 ANA30 VCI30 V*30 VM30 ANA21 VCI21 V*21 VM21 ANA20 VCI20 V*20 VM20
For definition see GCI Channels Definition Register above. VIII.20 - GCI Channels Definition Register 2 - GCIR2 (26)H
bit15 TDM5 GCI CHANNEL 5 After reset (0000)H TDM4 bit8 bit7 TDM5 GCI CHANNEL 4 TDM4 bit 0 ANA51 VCI51 V*51 VM51 ANA50 VCI50 V*50 VM30 ANA41 VCI41 V*41 VM41 ANA40 VCI40 V*40 VM40
For definition see GCI Channels Definition Register above. VIII.21 - GCI Channels Definition Register 3 - GCIR3 (28)H
bit15 TDM5 GCI CHANNEL 7 After reset (0000)H TDM4 bit8 bit7 TDM5 GCI CHANNEL 6 TDM4 bit 0 ANA71 VCI71 V*71 VM71 ANA70 VCI70 V*70 VM70 ANA61 VCI61 V*61 VM61 ANA60 VCI60 V*60 VM60
For definition see GCI Channels Definition Register above.
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VIII - INTERNAL REGISTERS (continued) VIII.22 - Transmit Command / Indicate Register - TCIR (2A)H
bit15 D G0 CA2 CA1 CA0 READ 0 bit8 0 bit7 Nu Nu C6A bit 0 C5/E C4/S1 C3/S2 C2/S3 C1/S4
After reset (00FF)H
When this register is written by the microprocessor, these different bits mean : READ : READ C/I MEMORY READ = 1, READ C/I MEMORY. READ = 0, WRITE C/I MEMORY. CA 0/2 : TRANSMIT COMMAND/INDICATE MEMORY ADDRESS CA 0/2 : These bits define one of eight Command/Indicate Channels. G0 : This bit defines one of two GCI MULTIPLEXy. G0 = 0, GCI0 (DIN4/DOUT4) is selected. G0 = 1, GCI1 (DIN5/DOUT5) is selected. D : Destination; this bit defines the destination of bits 0 to 5. D=0: the primitive C6 to C1 is transmitted directly into one of 16 GCI channels defined by G0 and CA 0/2. D=1: the 6 bit word A, E, S1, S2, S3, S4 is put instead of the six bits received latest during the timeslot 4n+3 (GCI channel defined by G0 and CA 0/2) and these 6 bit word is transmitted into any selected output timeslot after switching.
bit15 D=0 D=0 G0 G0 CA2 CA2 CA1 CA1 CA0 CA0 READ READ Nu Nu bit8 Nu Nu bit7 Nu Nu Nu Nu C6 A C5 E C4 S1 C3 S2 C2 S3 bit 0 C1 S4
C6/1
: New Primitive to be transmitted to the selected GCI channel (DOUT4 or DOUT5). Case of D=0. C6 is transmitted first if ANA=1. C4 is transmitted first if ANA=0.
A, E, S1 to S4: New 6 bit word to be transmitted into any output timeslot. Case of D=1. The New Primitive (or the 6 bit word) is taken into account by the transmitter after writing bits 8 to 15 (if 8bit microprocessor). Transmit Command/Indicate Register (after reading)
bit15 D=0 D=1 G0 G0 CA2 CA2 CA1 CA1 CA0 CA0 READ READ Nu Nu bit8 Nu Nu bit7 PT1 PT1 PT0 PT0 C6 A C5 E C4 S1 C3 S2 C2 S3 bit 0 C1 S4
When this register is read by the microprocessor, these different bits mean : READ : READ C/I MEMORY READ = 1, READ C/I MEMORY. READ = 0, WRITE C/I MEMORY. CA 0/2 : TRANSMIT C/I ADDRESS CA 0/2 : These bits define one of eight Command/Indicate Channels. G0 : This bit defines one of two GCI multiplexes. G0 = 0, DIN4/DOUT4 are selected. G0 = 1, DIN5/DOUT5 are selected. D : Destination. This bit defines the destination of bits 0 to 5 D=0: the destination is one of 16 GCI channels defined by G0 and CA 0/2. D=1:the destination is any TDM (after switching). C6/1 : Last Primitive transmitted. Case of D=1
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VIII - INTERNAL REGISTERS (continued) A, E, S1 to S4: 6 bit word transmitted. Case of D=1. PT0/1 : Status bits
P1 0 0 1 1 P0 0 1 0 1 Primitive (or 6 bit word) has Primitive (or 6 bit word) has Primitive (or 6 bit word) has Primitive (or 6 bit word) has Primitive Status not been transmitted yet. been transmitted once. been transmitted twice. been transmitted three times or more.
VIII.23 - Transmit Monitor Address Register - TMAR (2C)H
bit15 0 G0 MA2 MA1 MA0 READ Nu bit8 Nu bit7 Nu Nu TIV FABT L NOB 0 bit 0 Nu
After reset (000F)H
When this register is written by the microprocessor, these different bits mean : READ : READ MON MEMORY READ=1, READ MON MEMORY. READ=0, WRITE MON MEMORY. MA 0/2 : TRANSMIT MONITOR ADDRESS MA 0/2 :These bits define one of eight Monitor Channel if validated. G0 : This bit defines one of two GCI multiplexes. G0 = 0, TDM4 is selected. G0 = 1, TDM5 is selected. NOB : NUMBER OF BYTE to be transmitted NOB = 1, One byte to transmit. NOB = 0, Two bytes to transmit. L : Last byte L = 1, the word (or the byte) located in the Transmit Monitor Data Register (TMDR) is the last. L = 0, the word (or the byte) located in the Transmit Monitor Data Register (TMDR) is not the last. FABT : FABT = 1, the current message is aborted by the transmitter. TIV : Timer interrupt is Validated TIV = 1, Time Out alarm generates an interrupt when the timer has expired. TIV = 0, Time Out alarm is masked. If 8 bit microprocessor the Data (TMDR Register) is taken into account by the transmitter after writing bits 8 to 15 of this register. Transmit Monitor Address Register (after reading)
bit15 0 G0 MA2 MA1 MA0 READ Nu bit8 Nu bit7 Nu Nu TO ABT L NOBT EXE bit 0 IDLE
When this register is read by the microprocessor, these different bits mean : READ, MA0/2, G0 have same definition as already described for the write register cycle. IDLE EXE : When this bit is at "1", IDLE (all 1's) is transmitted during the channel validation. : EXECUTED When this status bit is at "1", the command written previously by the microprocessor has been executed and a new word can be stored in the Transmit Monitor Data Register (TMDR) by the microprocessor. When this bit is at "0", the command written previously by the microprocessor has not yet been executed.
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VIII - INTERNAL REGISTERS (continued) NOBT : NUMBER OF BYTE which has been transmitted. NOBT = 1, the first byte is transmitting. NOB T = 0, the second byte is transmitting, the first byte has been transmitted. L : Last byte ; this L bit is the L bit which has been written by the microprocessor. ABT : ABORT ABT=1, the remote receiver has aborted the current message. TO : Time Out one millisecond TO = 1, the remote receiver has not acknowledged the byte which has been transmitted one millisecond ago. VIII.24 - Transmit Monitor Data Register - TMDR (2E)H
bit15 M18 M17 M16 M15 M14 M13 M12 bit8 M11 bit7 M08 M07 M06 M05 M04 M03 M02 bit 0 M01
After reset (FFFF)H
M08/01 : First Monitor Byte to transmit. M08 bit is transmitted first. M18/11 : Second Monitor Byte to transmit if NOB = 0 (bit of TMAR). M18 bit is transmitted first. VIII.25 - Transmit Monitor Interrupt Register - TMIR (30)H
bit15 MI71 MI61 MI51 TDM5 MI41 MI31 MI21 MI11 bit8 MI01 bit7 MI70 MI60 MI50 TDM4 MI40 MI30 MI20 MI10 bit 0 MI00
After reset (0000)H
When the microprocessor read this register, this register is reset (0000)H. MIxy : Transmit Monitor Channel x Interrupt, Multiplex y with : 0 x 7, 1 of 8 GCI CHANNELS belonging to the same multiplex TDM4 or TDM5 y = 0, GCI CHANNEL belongs to the multiplex TDM4 and y = 1 to TDM5. MIxy = 1 when : - a word has been transmitted and pre-acknowledged by the Transmit Monitor Channel xy (In this case the Transmit Monitor Data Register (TMDR) is available to transmit a new word) or - the message has been aborted by the remote receive Monitor Channel or - the Timer has reached one millisecond (in accordance with TIV bit of TMAR) by IM3 bit of IMR. When MIxy goes to "1", the Interrupt MTX bit of IR is generated. Interrupt MTX can be masked.
VIII.26 - Memory Interface Configuration Register - MICR (32)H
bit15 P41 P40 P31 P30 P21 P20 P11 bit8 P10 bit7 Z W V U T S R bit 0 REF
After reset (E4F0)H
: MEMORY REFRESH REF = 1, DRAM REFRESH is validated, REF = 0, DRAM REFRESH is not validated. R,S,T : These three bits define the external RAM circuit organization (1word=2bytes) The cycle duration is always 15.625ms (512 periods of the clock applied on XTAL1 pin).
T 0 0 0 0 1 1 S 0 0 1 1 0 0 R 0 1 0 1 0 1 If refresh 128K x 8 SRAM circuit (up to 512K words) 512K x 8 SRAM circuit (up to 512K words) 256K x 16 DRAM circuit (up to 1M word) 1M x 4 (or 16) bits DRAM circuit (up to 4M words) 4M x 4 (or 16) bits DRAM circuit (up to 8M words) 101 to 111 not used (this writting is forbidden)
REF
512 cycles / 8ms 1024 cycles / 16ms 2048 cycles / 32ms
The cycle duration is always 15.625ms (512 periods of the clock applied on XTAL1 Pin).
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VIII - INTERNAL REGISTERS (continued) U,V,W,Z : These four bits define the different signals delivered by the MHDLC. First Case : the external RAM circuit is DRAM (T = 1 or S = 1) - U defines the time Tu comprised between beginning of cycle and falling edge of NRAS : U = 1, Tu = 60ns - U = 0, Tu = 30ns - V defines the time Tv comprised between falling edge of NRAS and falling edge of NCAS : V = 1, Tv = 60ns - V = 0, Tv = 30ns - W defines the time Tw comprised between falling edge of NCAS and rising edge of NCAS : W = 1, Tw = 60ns - W = 0, Tw = 30ns - Z defines the time Tz comprised between rising edge of NCAS and end of cycle : Z = 1, Tz = 60ns - Z = 0, Tz = 30ns The total cycle is Tu + Tv + Tw + Tz. The different output signals are high impedance during 15ns before the end of each cycle. Second Case : the external RAM circuit is SRAM (T = 0 or S = 0) - U and V define a part of write cycle for SRAM : the time Tuv comprised between falling edge and rising edge of NCE. The total of write cycle is : 15ns+Tuv + 15ns.
V 0 0 1 1 U 0 1 0 1 Tuv 30ns 60ns 90ns 120ns
- W and Z define a part of read cycle for SRAM : the time Twz comprised between falling edge of NOE and rising edge of NOE. The total of read cycle is : Twz +30ns
Z 0 0 1 1 W 0 1 0 1 Twz 30ns 60ns 90ns 120ns
N.B. The different output signals are high impedance during 15ns before the end of each cycle. On the outside of each (DRAM or SRAM) cycle all the outputs are high impedance or not in accordance with MBL bit (see "MBL : Memory Bus Low impedance").
Memory
bit15 bit8 bit7 Z W V U T S R bit 0 REF P4E1 P4E0 P3E1 P3E0 P2E1 P2E0 P1E1 P1E0
After reset (E4F0)H
P1 E0/1 : PRIORITY 1 for entity defined by E0/1 P2 E0/1 : PRIORITY 2 for entity defined by E0/1 P3 E0/1 : PRIORITY 3 for entity defined by E0/1 P4 E0/1 : PRIORITY 4 for entity defined by E0/1 Entity definition :
E1 0 0 1 1 E0 0 1 0 1 Entity Rx DMA Controller Microprocessor Tx DMA Controller Interrupt Controller
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VIII - INTERNAL REGISTERS (continued) PRIORITY 5 is the last priority for DRAM Refresh if validated. DRAM Refresh obtains PRIORITY 0 (the first priority) automatically when the first half cycle is spent without access to memory. After reset (E400)H, the Rx DMA Controller has the PRIORITY 1 the Microprocessor has the PRIORITY 2 the Tx DMA Controller has the PRIORITY 3 the Interrupt Controller has the PRIORITY 4 the DRAM Refresh has the PRIORITY 5 VIII.27 - Initiate Block Address Register - IBAR (34)H
bit15 A23 A22 A21 A20 A19 A18 A17 bit8 A16 bit7 A15 A14 A13 A12 A11 A10 A9 bit 0 A8
After reset (0000)H
A8/23 : Address bits. These 16 bits are the segment address bits of the Initiate Block (A8 to A23 for the external memory).The offset is zero (A0 to A7 ="0"). The Initiate Block Address (IBA) is :
23 8 7 0 A23 A22 A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A9 A8 0 0 0 0 0 0 0 0
The 23 more significant bits define one of 8 Megawords. (One word comprises two bytes.) The least significant bit defines one of two bytes when the microprocessor selects one byte. VIII.28 - Interrupt Queue Size Register - IQSR (36)H
bit15 TBFS 0 0 0 0 0v 0 bit8 0d bit7 HS2 HS1 HS0 MS2 MS1 MS0 CS1 bit 0 CS0
After reset (0000)H
CS0/1 : Command/Indicate Interrupt Queue Size These two bits define the size of Command/Indicate Interrupt Queue in external memory. The location is IBA + 256 + HDLC Queue size + Monitor Channel Queue Size (see The Initiate Block Address (IBA)). MS0/2 : Monitor Channel Interrupt Queue Size These three bits define the size of Monitor Channel Interrupt Queue in external memory. The location is IBA + 256 + HDLC Queue size. HS0/2 : HDLC Interrupt Queue Size These three bits define the size of HDLC status Interrupt Queue in external memory for each channel. The location is IBA+256 (see The Initiate Block Address (IBA))
HS2 0 0 0 0 1 1 1 1 HS1 0 0 1 1 0 0 1 1 HS0 0 1 0 1 0 1 0 1 HDLC Queue Size 128 words 256 words 384 words 512 words 640 words 768 words 896 words 1024 words MS2 0 0 0 0 1 1 1 1 MS1 0 0 1 1 0 0 1 1 MS0 0 1 0 1 0 1 0 1 MON Queue Size 128 words 256 words 384 words 512 words 640 words 768 words 896 words 1024 words CS1 0 0 1 1 CS0 0 1 0 1 C/I Queue Size 64 words 128 words 192 words 256 words
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VIII - INTERNAL REGISTERS (continued) TBFS : Time Base running with Frame Synchronisation signal TBFS=1, the Time Base defined by the Timer Register (see page 92) is running on the rising edge of Frame Synchronisation signal. TBFS=0, the Time Base defined by the Timer Register is running on the rising edge of MCLK signal. VIII.29 - Interrupt Register - IR (38)H
bit15 Nu Nu SFCO PRSR TIM bit8 bit7 Rx FOV Rx ICOV FWAR bit 0 MTX MRX C/IRX HDLC INT INT Tx Tx FOV FWAR FOV FWAR
After reset (0000)H
This register is read only. When this register is read by the microprocessor, this register is reset (0000)H. If not masked, each bit at "1" generates "1" on INT0 pin. HDLC : HDLC INTERRUPT HDLC = 1, Tx HDLC or Rx HDLC has generated an interrupt The status is in the HDLC queue. C/IRX : Command/Indicate Rx Interrupt C/IRX = 1, Rx Commande/Indicate has generated an interrupt. The status is in the HDLC queue. MRX : Rx MONITOR CHANNEL INTERRUPT MRX = 1, one Rx MONITOR CHANNEL has generated an interrupt.The status is in the Rx Monitor Channel queue. MTX : Tx MONITOR CHANNEL INTERRUPT MTX = 1, one or several Tx MONITOR CHANNELS have generated an interrupt. Transmit Monitor Interrupt Register (TMIR) indicates the Tx Monitor Channels which have generated this interrupt. ICOV : INTERRUPT CIRCULAR OVERLOAD ICOV = 1, One of three circular interrupt memories is completed. RxFWAR : Rx DMA CONTROLLER FIFO WARNING RxFWAR = 1, Rx DMA CONTROLLER has generated an interrupt, its fifo is 3/4 completed. RxFOV : Rx DMA CONTROLLER FIFO OVERLOAD RxFOV = 1, Rx DMA CONTROLLER has generatedan interrupt,it cannot transfer data from Rx HDLC to external memory, its fifo is completed. TxFWAR : Tx DMA CONTROLLER FIFO WARNING TxFWAR = 1, Tx DMA CONTROLLER has generated an interrupt, its fifo is 3/4 completed. TxFOV : Tx DMA CONTROLLER FIFO OVERLOAD TxFOV = 1, Tx DMA CONTROLLER has generated an interrupt, it cannot transfer data from Tx HDLC to external memory, its fifo is completed. INTFWAR : INTERRUPT CONTROLLER FIFO WARNING INTFWAR = 1, INTERRUPT CONTROLLER has generated an interrupt, its fifo is 3/4 completed. INTFOV : INTERRUPT CONTROLLER FIFO OVERLOAD INTFOV = 1, INTERRUPT CONTROLLER has generated an interrupt, it cannot transfer status from DMA and GCI controllers to external memory, its internal fifo is completed. TIM : TIMER TIM = 1, the programmable timer has generated an interrupt.
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VIII - INTERNAL REGISTERS (continued) PRSR : Pseudo Random Sequence Recovered PRSR = 1,the Pseudo Random Sequence transmitted by the generator has been recovered by the analyzer. : Sequence Fault Counter Overload SFCO = 1, the Fault Counter has reached the value (00FF)H.
SFCO
VIII.30 - Interrupt Mask Register - IMR (3A)H
bit15 Nu Nu IM13 IM12 IM11 IM10 IM9 bit8 IM8 bit7 IM7 IM6 IM5 IM4 IM3 IM2 IM1 bit 0 IM0
After reset (FFFF)H
IM13/0 : INTERRUPT MASK 0/7 When IM0 = 1, HDLC bit is masked. When IM1 =1, C/IRX bit is masked. When IM2 = 1, MRX bit is masked. When IM3 = 1, MTX bit is masked. When IM4 = 1, ICOV bit is masked When IM5 = 1, RxFWAR bit is masked. When IM6 = 1, RxFOV bit is masked. When IM7 = 1, TxFWAR bit is masked. When IM8 = 1, TxFOV bit is masked. When IM9 = 1, INTFWAR bit is masked. When IM10 = 1, INTFOV bit is masked. When IM11 = 1, TIM bit is masked. When IM12 = 1, PRSR bit is masked. When IM13 = 1, SFCO bit is masked. VIII.31 - Timer Register - TIMR (3C)H
bit15 S3 S2 S1 0 to 15s bit12 S0 MS9 MS8 MS7 MS6 MS5 MS4 MS3 MS2 MS1 0 to 999ms After reset (0800)H id 512ms bit0 MS0 bit1 MM1 bit 0 MM0
0 to 3x0.25ms
This programmable register indicates the time at the end of which the Watch Dog delivers logic "1" on the pin WDO (which is an output) but only if the microprocessor does not reset the counter assigned (with the help of WDR bit of IDCR Identification and Dynamic Command Register) during the time defined by the Timer Register. The Timer Register and its counter can be used as a time base by the microprocessor. An interrupt (TIM) is generated at each period defined by the Timer Register if the microprocessor does not reset the counter with the help of WDR (bit of IDCR). The Watch Dog or the Timer is incremented by the Frame Synchronisation clock (TBFS=1) or by a submultiple of MCLK signal (TBFS=0; TBFS, bit of Interrupt Queue Size Register). When TSV=1{Time Stamping Validated (GCR)} this programmable register is not used. VIII.32 - Test Register - TR (3E)H
bit15 bit8 bit7 bit 0
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IX - EXTERNAL REGISTERS These registers are located in shared memory. Initiate Block Address Register (IBAR) gives the Initiate Block Address (IBA) in shared memory (see Register IBAR(34)H on Page 90). `Not used' bits (Nu) are accessible by the microprocessor but the use of these bits by software is not recommended. IX.1 - Initialization Block in External Memory
Descriptor Address Channel T CH 0 R T CH1 R Address IBA+00 IBA+02 IBA+04 IBA+06 IBA+08 IBA+10 IBA+12 IBA+14 IBA+16 to IBA+246 IBA+248 IBA+250 IBA+252 IBA+254 Not used Not used TDA High RDA High bit15 Not used Not used Not used Not used bit8 bit7 TDA High RDA High TDA High RDA High bit0
Transmit Descriptor Address (TDA Low) Receive Descriptor Address (RDA Low) Transmit Descriptor Address (TDA Low) Receive Descriptor Address (RDA Low)
CH 2 to CH30
T CH 31 R
Transmit Descriptor Address (TDA Low) Receive Descriptor Address (RDA Low)
When Direct Memory Access Controller receives Start from one of 64 channels,it reads initialization block immediately to know the first address of the first descriptor for this channel. Bit 0 of Transmit Descriptor Address (TDA Low) and bit 0 of Receive Descriptor Address (RDA Low), are at ZERO mandatory. This Least Significant Bit is not used by DMA Controller, The shared memory is always a 16 bit memory for the DMA Controller. N.B. If several descriptors are used to transmit one frame then before transmitting frame, DMA Controller stores the address of the first Transmit Descriptor Address into this Initialization Block.
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IX - EXTERNAL REGISTERS (continued) IX.2 - Receive Descriptor This receive descriptor is located in shared memory. The quantity of descriptors is limited by the memory size only.
15 RDA+00 RDA+02 RDA+04 RDA+06 RDA+08 RDA+10 FR ABT OVF Not used FCRC 14 13 IBC 12 EOQ Not used Receive Buffer Address Low (16 bits) NRDA High (8 bits) Number of Bytes Received (NBR) Next Receive Descriptor Address Low (16 bits) 11 10 9 8 7 6 5 4 3 2 1 0 0 Size Of the Buffer (SOB) RBA High (8 bits)
The 5 first words located in shared memory to RDA+00 from RDA+08 are written by the microprocessor and read by the DMAC only. The 6th word located in shared memory in RDA+10 is written by the DMAC only during the frame reception and read by the microprocessor. SOB : Size Of the Buffer associated to descriptor up to 2048 words (1 word = 2 bytes). If SOB = 0, DMAC goes to next descriptor. RBA : Receive Buffer Address. LSB of RBA Low is at Zero mandatory. RDA : Receive Descriptor Address. NRDA : Next Receive Descriptor Address. LSB of NRDA Low is at Zero mandatory. NBR : Number of Bytes Received (up to 4096). IX.2.1 - Bits written by the Microprocessor only IBC : Interrupt if the buffer has been completed. IBC=1, the DMAC generates an interrupt if the buffer has been completed. EOQ : End Of Queue. EOQ=1, the DMAC stops immediately its reception generates an interrupt (HDLC = 1 in IR) and waits a command from the HRCR (HDLC Receive Command Register). EOQ=0, the DMAC continues. IX.2.2 - Bits written by the Rx DMAC only
FR 1 1 0 0 0 0 0 ABT 0 0 0 0 1 1 1 OVF 0 0 0 0 0 1 0 FCRC 0 1 0 0 0 0 1 Definition The frame has been received without error. The end of frame is in this buffer. The frame has been received with false CRC. If NBR is different to 0, the buffer related to this descriptor is completed.The end of frame is not in this buffer. If NBR is equal to 0, the Rx DMAC is receiving a frame. ABORT. The received frame has been aborted by the remote transmitter or the local microprocessor. OVERFLOW of FIFO. The received frame has been aborted. The received frame had not an integer of bytes.
IX.2.3 - Receive Buffer Each receive buffer is defined by its receive descriptor. The maximum size of the buffer is 2048 words (1 word=2 bytes)
15 RBA RBA+SOB-2 SECOND BYTE LOCATION LAST BYTE LOCATION AVAILABLE in the Receive Buffer 8 7 FIRST BYTE LOCATION THIRD BYTE LOCATION LAST - 1 BYTE LOCATION AVAILABLE in the Receive Buffer 0
Note: for Motorola processors, a swap may be necessary to read/write the Receive Buffer.
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IX - EXTERNAL REGISTERS (continued) IX.3 - Transmit Descriptor This transmit descriptor is located in shared memory. The quantity of descriptors is limited by the memory size only.
15 TDA+00 TDA+02 TDA+04 TDA+06 TDA+08 TDA+10 CFT ABT UND Not used BINT 14 BOF 13 EOF Not used 12 EOQ 11 10 9 8 7 6 5 4 3 2 1 0 Number of Bytes to be Transmitted (NBT) CRC PRI C Transmit Buffer Address Low (16 bits) NTDA High (8 bits) Next Transmit Descriptor Address Low (16 bits) TBA High (8 bits)
The 5 first words located in shared memory to TDA+00 from TDA+08 are written by the microprocessor and read by the DMAC only. The 6th word located in shared memory in TDA+10 is written by the DMAC only during the frame reception and read by the microprocessor. NBT : Number of Bytes to be transmitted (up to 4096). TBA : Transmit Buffer Address. LSB of TBA Low is at Zero mandatory. TDA : Transmit Descriptor Address. NTDA : Next Transmit Descriptor Address. LSB of NTDA Low is at Zero mandatory. IX.3.1 - Bits written by the Microprocessor only : Interrupt at the end of the frame or when the buffer is become empty. BINT = 1, if EOF = 1 the DMAC generates an interrupt when the frame has been transmitted ; if EOF = 0 the DMAC generates an interrupt when the buffer is become empty. BINT = 0, the DMAC does not generate an interrupt during the transmission of the frame. BOF : Beginning Of Frame BOF = 1,thetransmit buffer associated to this transmitdescriptor contains the beginning of frame. The DMA Controller will store automatically the current descriptor address in the Initialization Block. BOF = 0, the DMA Controller will not store the current descriptor address in the Initialization Block. EOF : End Of Frame EOF = 1,the transmit buffer associated to this transmit descriptor contains the end of frame. EOF = 0,the transmit buffer associated to this transmit descriptor does not contain the end of frame. EOQ : End Of Queue EOQ = 1, the DMAC stops immediately its transmission, generates an interrupt (HDLC = 1 in IR) and waits a command from the HTCR (HDLC Transmit Command Register). EOQ = 0, the DMAC continues. CRCC : CRC Corrupted CRCC = 1,at the end of this frame the CRC will be corrupted by the Tx HDLC Controller. PRI : Priority Class 8 or 10 PRI = 1, if CSMA/CR is validated for this channel, the priority class is 8. PRI = 0, if CSMA/CR is validated for this channel the priority class is 10. (see Register CSMA) BINT
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IX - EXTERNAL REGISTERS (continued) IX.3.2 - Bits written by the DMAC only CFT : Frame correctly transmitted CFT = 1, the Frame has been correctly transmitted. CFT = 0, the Frame has not been correctly transmitted. : Frame Transmitting Aborted ABT = 1, the frame has been aborted by the microprocessor during the transmission. ABT = 0, the microprocessor has not aborted the frame during the transmission. : Underrun UND = 1, the transmit FIFO has not been fed correctly during the transmission. UND = 0, the transmit FIFO has been fed correctly during the transmission.
ABT
UND
IX.3.3 - Transmit Buffer Each transmit buffer is defined by its transmit descriptor. The maximum size of the buffer is 2048 words (1 word=2 bytes)
TBA TBA + x ; NBT is odd : x = NBT - 1 NBT is even : x = NBT - 2 15 8 SECOND BYTE TO TRANSMIT LAST BYTE TO TRANSMIT if NBT is even 7 FIRST BYTE TO TRANSMIT THIRD BYTE TO TRANSMIT LAST BYTE TO TRANSMIT if NBT is odd 0
Note: for Motorola processors, a swap may be necessary to read/write the Receive Buffer. IX.4 - Receive & Transmit HDLC Frame Interrupt
bit15 NS 0 Tx A4 A3 A2 A1 bit8 A0 bit7 0 0 0 CFT/CFR BE/BF HALT EOQ bit 0 RRLF/ERF
This word is located in the HDLC interrupt queue ; IQSR Register indicates the size of this HDLC interrupt queue located in the external memory. NS : New Status. Before writing the features of event in the external memory the Interrupt Controller reads the NS bit : if NS = 0, the Interrupt Controller puts this bit at `1' when it writes the status word of the frame which has been transmitted or received. if NS = 1, the Interrupt Controller puts ICOV bit at `1' to generate an interrupt (IR Register). When the microprocessor has read the status word, it puts this bit at `0' to acknowledge the new status. This location becomes free for the Interrupt Controller. Transmitter Tx : Tx = 1, Transmitter A4/0 : Tx HDLC Channel 0 to 31 RRLF : Ready to Repeat Last Frame In consequenceof event such as Abort Command HDLC, Controller is waiting Start or Continue. EOQ : End of Queue The Transmit DMA Controller (or the Receive DMA Controller) has encountered the current Descriptor with EOQ at "1". DMA Controller is waiting "Continue" from microprocessor. HALT : The Transmit DMAController has receivedHALTfrom the microprocessor; it is waiting"Continue" from microprocessor. BE : Buffer Empty If BINT bit of Transmit Descriptor is at `1', the Transmit DMA Controller puts BE at "1" when the buffer has been emptied. CFT : Correctly Frame Transmitted A frame has been transmitted. This status is provided only if BINT bit of Transmit Descriptor is at `1'. CFT is located in the last descriptor if several descriptors are used to define a frame.
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IX - EXTERNAL REGISTERS (continued) Receiver Tx : Tx = 0, Receiver A4/0 : Rx HDLC Channel 0 to 31 ERF : Error detected on Received Frame An error such as CRC not correct, Abort, Overflow has been detected. EOQ : End of Queue The receive DMA Controller has encountered the current receive Descriptor with EOQ at "1". DMA Controller is waiting "Continue" from microprocessor. HALT : The Receive DMA Controller has received HALT or ABORT (on the outside of frame) from the microprocessor; it is waiting "Continue" from the microprocessor. BE : Buffer Filled If IBC bit of Receiver Descriptor is at `1', the Receive DMA Controller puts BF at"1" when it has filled the current buffer with data from the received frame. CFR : Correctly Frame Received A receive frame is ended with a correctCRC. Theend of the frame is located in the last descriptor if several Descriptors. IX.5 - Receive Command / Indicate Interrupt IX.5.1 - Receive Command / Indicate Interrupt when TSV = 0 Time Stamping not validated (bit of GCR Register)
bit15 NS Nu S1 S0 G0 A2 A1 bit8 A0 bit7 Nu Nu C6/A bit 0 C5/E C4/S1 C3/S2 C2/S3 C1/S4
This word is located in the Command/Indicate interrupt queue ; IQSR Register indicates the size of this interrupt queue located in the external memory. NS : New Status. Before writing the features of event in the external memory the Interrupt Controller reads the NS bit : if NS = 0, the Interrupt Controller puts this bit at `1' when it writes the new primitive which has been received. if NS = 1, the Interrupt Controller puts INTFOV bit at `1' to generate an interrupt (IR Interrupt Register). When the microprocessor has read the status word, it puts this bit at `0' to acknowledge the new status. This location becomes free for the Interrupt Controller. S0/S1 Source of the event:
S1 0 0 0 0 1 1 1 S0 0 0 1 1 0 0 1 G0 0 1 0 1 0 1 X Word stored in shared memory Primitive C1/6 received from GCI Multiplex 0 corresponding to DIN4 Primitive C1/6 received from GCI Multiplex 1 corresponding to DIN5 A, E, S1/S4 bits from any input timeslot switched to one timeslot 4n+3 of GCI 0 without outgoing to DOUT4 A, E, S1/S4 bits from any input timeslot switched to one timeslot 4n+3 of GCI 1 without outgoing to DOUT5 AIS detected during more 30 ms from any input timeslot and switched to B1, B2 channels (16 bits) of the GCI 0 (DOUT4) in transparent mode or not AIS detected during more 30 ms from any input timeslot and switched to B1, B2 channels (16 bits) of the GCI 1 (DOUT5) in transparent mode or not. Reserved
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IX - EXTERNAL REGISTERS (continued) G0 : This bit defines one of two GCI y (DIN4/DOUT4 or DIN5/DOUT5). G0 = 0, GCI0 (DIN4/DOUT4) is the source. G0 = 1, GCI1 (DIN5/DOUT5) is the source. A2/0 : GCI Channel 0 to 7 belonging to GCI 0 or GCI 1. C6/1 : New Primitive received twice consecutively. Case of S0=S1=0. A, E, S1/S4 bits received twice consecutively. Case of S0 = 1 S1 = 0. Bit0/5 are not Significant when S0 = 0, S1 = 1. IX.5.2 - Receive Command / Indicate Interrupt when TSV = 1 Time Stamping validated (bit of GCR Register)
bit15 NS T15 Nu T14 Nu T13 Nu T12 G0 T11 A2 T10 A1 T9 bit8 A0 T8 bit7 Nu T7 Nu T6 C6/A T5 T4 T3 T2 T1 bit 0 C5/E C4/S1 C3/S2 C2/S3 C1/S4 T0
These two words are located in the Command/Indicate interrupt queue. First word see definition above. T0/15: binary counter value when a new primitive is occured. IX.6 - Receive Monitor Interrupt IX.6.1 - Receive Monitor Interrupt when TSV = 0 TSV : Time Stamping not Validated (bit of GCR Register)
bit15 NS M18 M17 M16 M15 G0 M14 A2 M13 A1 M12 bit8 A0 M11 M8 M7 M6 M5 bit7 ODD M4 A M3 F M2 bit 0 L M1
These two words are transferred into the Monitor interrupt queue ; IQSR Register indicates the size of this interrupt queue located in the external memory. NS : New Status. Before writing the features of event in the external memory the Interrupt Controller reads the NS bit : if NS = 0, the Interrupt Controller stores two new bytes M1/8 and M11/18 then puts NS bit at `1' when it writes the status of these two bytes which has been received. if NS = 1, the Interrupt Controller puts ICOV bit at `1' to generate an interrupt (IR Register). G0 : G0 = 0, GCI 0 corresponding to DIN4 input and DOUT4 output. G0 = 1, GCI 1 corresponding to DIN5 input and DOUT5 output. L : Last byte L=1, two cases: if ODD = 1, the following word of the Interrupt Queue contains the Last byte of message if ODD =0, the previous word of the Interrupt Queue (concerning this channel) contains the Last byte of message. L = 0, the following word and the previous word does not contains the Last byte of message. F : First byte F=1, the following word contains the First byte of message. F=0, the following word does not contain the First byte of message. A : Abort A=1, Received message has been aborted.
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IX - EXTERNAL REGISTERS (continued) : Odd byte number ODD = 1, one byte has been written in the following word. ODD = 0, two bytes have been written in the following word. In case of V* protocol ODD,A,F,L bits are respectively 1,0,1,1. M1/8 : New Byte received twice consecutively if GCI Protocol has been validated. Byte received once if V* Protocol has been validated. M11/18 : Next new Byte received twice consecutively if GCI Protocol has been validated. This byte is at "1" in case of V* protocol. IX.6.2 - Receive Monitor Interrupt when TSV = 1 TSV : Time Stamping Validated (bit of GCR Register)
bit15 NS M18 T15 0 M17 T14 0 M16 T13 0 M15 T12 0 G0 M14 T11 0 A2 M13 T10 0 A1 M12 T9 0 bit8 A0 M11 T8 0 M8 T7 0 M7 T6 0 M6 T5 0 M5 T4 0 bit7 ODD M4 T3 0 A M3 T2 0 F M2 T1 0 bit 0 L M1 T0 0
ODD
These four words are located in the Monitor interrupt queue ; IQSR Register indicates the size of this interrupt queue located in the external memory. NS : New Status. Before writing the features of event in the external memory the Interrupt Controller reads the NS bit : if NS = 0, the Interrupt Controller stores two new bytes M1/8 and M11/18 then puts NS bit at `1' when it writes the status of these two bytes which has been received. if NS = 1, the Interrupt Controller puts ICOV bit at `1' to generate an interrupt (IR Register). G0 : G0 = 0, GCI 0 corresponding to DIN4 input and DOUT4 output. G0 = 1, GCI 1 corresponding to DIN5 input and DOUT5 output. L : Last byte L=1, two cases: if ODD = 1, the following word of the Interrupt Queue contains the Last byte of message if ODD =0, the Last byte of message has been stored at the previous access of the Interrupt Queue (concerning this channel). L=0, the following word and the previous word does not contain the Last byte of message. F : First byte F=1, the following word contains the First byte of message. F=0, the First byte of message is not the following word. A : Abort A=1, Received message has been aborted. ODD : Odd byte number ODD = 1, one byte has been written in the following word. ODD = 0, two bytes have been written in the following word. M1/8 : New Byte received twice consecutively if GCI Protocol has been validated. Byte received once if V* Protocol has been validated. M11/18 : Next new Byte received twice consecutively if GCI Protocol has been validated. This byte is at "1" in case of V* protocol. T15/0 : Binary counter value when a new primitive is occurred.
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X - PQFP160 PACKAGE MECHANICAL DATA
Dimensions A A1 A2 B C D D1 D3 e E E1 E3 L L1 K Min. 0.25 3.17 0.22 0.13 30.95 27.90 Millimeters Typ. Max. 4.07 3.67 0.38 0.23 31.45 28.10 Min. 0.010 0.125 0.009 0.005 1.219 1.098 Inches Typ. Max. 0.160 0.144 0.015 0.009 1.238 1.106
3.42
0.135
30.95 27.90 0.65
31.20 28.00 25.35 0.65 31.20 28.00 25.35 0.80 1.60
31.45 28.10 0.95
1.219 1.098 0.026
1.228 1.102 0.998 0.026 1.228 1.102 0.998 0.0315 0.063
1.238 1.106 0.0374
0o (Min.), 7o (Max.)
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Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specification mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics (c) 1999 STMicroelectronics - Printed in Italy - All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia - Brazil - China - Finland - France - Germany - Hong Kong - India - Italy - Japan - Malaysia - Malta - Morocco Singapore - Spain - Sweden - Switzerland - United Kingdom - U.S.A. http://www.st.com
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